Make a rule called all to compile and link in once file called "dinam" all files .c.
I have tried:
All:
gcc -c *.c
I need to kink all .o in one file.
This will suffice:
dinam:
gcc -c *.c
gcc *.o -o dinam
You can write more sophisticated makefiles when you are ready.
Related
My makefile have two lines:
Rule_1
File.o : File.cpp
g++ -c File.cpp -o File.o
Rule_2
File : File.o
g++ File.o -o File
I want any change in File.cpp leads to regeneration of both File.o and File. This is done by:
Makfile:
Rule_2
Rule_1
But the following does not work and only regenerates File.o
Rule_1
Rule_2
Why? I note that, I am not using any all: in my makefile. With all: File both methods above work.
I assume your make tool is GNU Make.
Unless you specify targets on the commandline, like:
make File
make will by default attempt to make the first target
in the makefile, which in your problem case is File.o.
See How make Processes a Makefile
When you add:
all: File
at the top, all is the first target, which depends on File,
which in turn depends on File.o.
And I suggest you replace that with:
.PHONY: all
all: File
See Phony targets
I want to be able to turn all the *.asm files in a folder to *.o files. For example, if I have header.asm and main.asm, I want header.o and main.o. Nasm can only assemble 1 input file to 1 output file.
I have tried this:
%.o : %.asm
nasm -f elf64 $(patsubst %.o,%.asm,$#) -o $#
along with multiple other things but to no success.
Somewhere you have to tell make what files you want to assemble. A pattern rule is just a template for how to build a .o from a .asm. It's not an instruction that says "go find all .asm files and turn them into .o files". It's a template that says, IF you want to build a .o file, and you can find a .asm file, then here's how you can turn the latter into the former.
So, you need a pattern rule to describe how to build things:
%.o : %.asm
nasm -f elf64 $< -o $#
then you also need a list of the things you want to build; say:
all: foo.o bar.o baz.o
(since you haven't told us anything about the names of the .asm files you want to build I just used random names).
Just to review the terminology, this is the structure of a makefile 'rule':
target: dependencies ...
commands
...
This is the makefile I've written:
CC = mpicc
SHAREDLIB = libfmd.so
CFLAGS = -fPIC -Wall -Wno-unused-result -O3 -fopenmp
LFLAGS = -lm -fopenmp -lgsl -lgslcblas
OBJS = $(patsubst %.c,%.o,$(wildcard *.c))
.PHONY: all shared clean
all: shared
shared: $(SHAREDLIB)
$(SHAREDLIB): depend.mk $(OBJS)
$(CC) $(OBJS) -shared -o $# $(LFLAGS)
depend.mk: *.c *.h
$(CC) -MM *.c > depend.mk
-include depend.mk
clean:
rm -f *.o libfmd.so depend.mk
When the folder is clean, and I enter make clean, the following lines are shown:
mpicc -MM *.c > depend.mk
rm -f *.o libfmd.so depend.mk
It seems to me that -include depend.mk in addition to including depend.mk, executes the rule that depend.mk is its target. I'd like to stop this behavior.
You are correct. See How Makefiles are Remade in the documentation.
There is no way to prevent this behavior: if there's a rule that creates an included makefile, make will always rebuild it if it's out of date, then re-invoke itself to read the latest version.
The question is, why do you want to avoid it? Maybe if you explained the behavior you are actually looking for at a higher level we could help. As you have it here it's possible for .o files to be created without any depend.mk file created, then a compile fails, you modify a header file to fix it, but since the depend.mk file doesn't exist when you re-run make the source files are not rebuilt properly.
If you want to get accurate handling of C/C++ dependencies with GCC you might take a look at Auto-Dependency Generation.
depend.mk: *.c *.h
$(CC) -MM *.c > depend.mk
FYI, this is wrong, as make doesn't support shell wildcards in a rule string. Although on a recipe line that could work as it gets expanded by the shell itself.
I'd like to stop this behavior
depend.mk is a prerequisite of the default target, so it is a target anyway.
Also, preprocessing into depend.mk is slow for large projects, so it totally makes sense either to switch to manually written dependencies, or use a recommended way to generate them, as #MadScientist suggested.
I am using make which calls g++ always re-compiles the code, even when I do not change the source code. That happens for all my projects, even for simple ones such as:
[code]
all: main.cpp
g++ -std=c++11 -c main.cpp
[/code]
I believe it should compare the date/time on source and object code. Could some help me with this, I am running using GNU toolchain on Ubuntu 12.04
THX
Edit: sorry guys, I do use Makefile, I edited my question accordingly.
Simplest Makefile
It was already pointed out that your Makefile is probably wrong. The 'all' target is indeed always built (although it may result in a no-op if it has no commands and all dependencies are already satisfied). All you need in your makefile is this:
all: main
Object files
If you expect to have more source file in your build, you should consider creating intermediate object files:
all: main
main: main.o
Tweak the build
Make will automatically find the main.ccp file and turn it into main which is required per the directive above. You can use special make variables to further tweak the compilation, e.g. for debug information inclusion and for warning configuration:
CXXFLAGS = -g -Wall -Werror
all: main
main: main.o
Nitpicking
If you insist on building up the compile rule yourself, you can do it like this:
%.o: %.hpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -o $# -c $<
CXX: C++ compiler
CPPFLAGS: C preprocessor flags
CXXFLAGS: C++ compiler flags
$#: Target
$<: First dependency
If you don't want to use the standard variables nor pattern matching, you can build up the whole makefile explicitly:
all: main
main: main.o
gcc -o $# $^
main.o: main.c
gcc -g -Wall -Werror -o $# -c $<
$^: Use that one if you want to include all dependencies, for example if you have multiple *.o files to build one binary.
Note: It is a bad idea to write the file names directly into the command as you might forget to update them later.
all: main.cpp
g++ -std=c++11 -c main.cpp
This seems wrong. Why does the rule for all has main.cpp as its target? Shouldn't it be something.exe or something.o? Say
all: main.exe
main.exe: main.cpp
g++ -std=c++11 main.cpp -o main.exe
clean:
del main.exe
Targets are output files and cpp files are source code which should be input to the make system.
g++ would have to "recompile" in general (what happens if you change the header but not main.cpp?)
If you are concerned about long build times, you should use something like Make (which is designed specifically to avoid recompiling when the source hasn't changed)
The compiler will always compile the code. If you want to do conditional compilation (based on file times etc) you will need to use a make system such as Make, CMake, Ant, etc. For the simplest you can set up a small "Makefile" in the directory and use the command "make" to build.
Simple Makefile for compiling "myapp.exe" from "main.cpp", "file1.cpp" and "file2.cpp"
myapp.exe: main.o file1.o file2.o
g++ -o myapp.exe main.o file1.o file2.o
(make knows to use .cpp files to build .o files)
But if you also have header files, then you will need to build dependency chains, for which you may want to look into something more sophisticated like automake, cmake, ant, etc.
---- EDIT ----
Based on your updated post, the problem is that you aren't specifying a target, so Make has to assume it needs to recompile. See my example in the above answer.
Say I have the following rule in my Makefile:
foo: foo1.c foo2.c head1.h head2.h
gcc -o $# foo1.c foo2.c
As you can see, in this case - as in most cases- the .c files in the rule correspond to the .c files you pass to gcc. My question is, is there a variable that can be passed to a Makefile which would evaluate to "all the .c files in the rule"?
Personally, I use the following:
CFILES=$(filter %.c,$^)
foo: foo1.c foo2.c head1.h head2.h
gcc -o $# $(CFILES)
but I'm not sure if this is the correct way...
I guess your filter is fine, but I'd rather define separately the lists of .c and .h files and use those lists where appropriate:
CFILES=foo1.c foo2.c
HFILES=head1.h head2.h
foo: $(CFILES) $(HFILES)
gcc -o $# $(CFILES)
If you don't mix .c and .h in the first place, there's no need to separate them afterwards.