I have a gnu make target to build with profiling information. I would like to print instructions to the user how to generate the coverage report when make has finished, that is after the last line of output from make.
Example:
$ make coverage
/usr/bin/g++ --coverage ....
...
make[1]: Leaving directory
<I want to print instructions here!>
$
Is there a way to accomplish this? How?
Just add an #echo statement at the end of your tasks. Like this:
coverage:
# do your stuff
#echo foo bar
$ make coverage
foo bar
$
Related
I have a simple target in my Makefile:
file1:
touch $#
I can build this target using: make file1
It also builds if I say: make ./file1 ('file1' is up to date)
However if i say: make $HOME/file1 then it tells me:
make: Nothing to be done for '/home/jesaremi/file1'
Is there a way to get consistent results regardless of what path I use?
You could add another rule:
$(shell pwd)/%: %
#:
This will allow the file1 rule to work for "file1", "./file1", "/home/jesaremi/path_to_cwd/file1", "~jesaremi/path_to_cwd/file1" and "~/path_to_cwd/file1".
I write makefile, which structure like following
#... Configure basic flags for compiler
.PHONY: mk_mingw
mk_mingw:
# build with mingw(windows)
.PHONY: mk_gcc_linux
mk_gcc_linux:
# build in gcc(linux)
#... some auxiliary unit such as clear, test ...
Use the following command when building with mingw(windows)
#command 1
$ make mk_mingw
Use the following command when building with gcc(Linux)
#command 2
$ make mk_gcc_linux
I hope the above two commands are legal in my project.
mk_gcc_linux and mk_mingw are environment of compiler(I specified)
But following commands isn't:
#command 3
$ make
Because it's not specify environment of compiler after make command.
I want make to report an error and stop when this situation(command 3) happens.
How do I do in my makefile?
By default, make tries to build the very first target. So you can simply put this on top of your Makefile:
.PHONY: first
first:
#echo Environment not specified!
#false
# the rest of file is following...
But for me it doesn't look quite right. Probably, setting a variable, instead of a dedicated target, is better.
I have a configure script that generates a config.inc file containing some variable definitions and a makefile that imports those configurations using
include config.inc
The thing that bothers me is that if the user tries to run the makefile directly without first running configure they get an unhelpful error message:
makefile:2: config.inc: No such file or directory
make: *** No rule to make target 'config.inc'. Stop.
Is there a way for me to produce a better error message, instructing the user to first run the configure script, without resorting to the autoconf strategy of generating the full makefile from inside configure?
Sure, no problem; just do something like this:
atarget:
echo here is a target
ifeq ($(wildcard config.inc),)
$(error Please run configure first!)
endif
another:
echo here is another target
include config.inc
final:
echo here is a final target
Note this is definitely specific to GNU make; there's no portable way to do this.
EDIT: the above example will work fine. If the file config.inc exists, then it will be included. If the file config.inc does not exist, then make will exit as it reads the makefile (as a result of the error function) and never get to the include line so there will be no obscure error about missing include files. That's what the original poster asked for.
EDIT2: Here's an example run:
$ cat Makefile
all:
#echo hello world
ifeq ($(wildcard config.inc),)
$(error Please run configure first!)
endif
include config.inc
$ touch config.inc
$ make
hello world
$ rm config.inc
$ make
Makefile:5: *** Please run configure first!. Stop.
I gave up and decided to use autoconf and automake to handle my makefile-generation needs.
All,
I'm trying to pass variables to make from the command line. My command is below
make ARCH=arm CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-g++
The error I received is
g++: error: arm: No such file or directory
But the file 'arm-openwrt-linux-g++' does exist.
I think the problem is I need to pass varibale to sub-make files. Can some help with an example of how to pass varialbes to sub-makefile from the command-line. I have tried using the -e and export options for make, but can't seen to get anything to work.
Thanks
Content of makefile:
# GNU Make solution makefile autogenerated by Premake
# Type "make help" for usage help
ifndef config
config=debug
endif
export config
PROJECTS := json openjaus
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
json:
#echo "==== Building json ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f json.make
openjaus: json
#echo "==== Building openjaus ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f openjaus.make
So, your problem is not related to sending variables over the command line.
Your problem is that in one of the makefiles in your sub-directories, which you haven't shown us, you're using the variable $(ARCH) in an incorrect way such that the expansion of the command line is not a legal g++ command line.
Based on the error message, most likely you're adding a space somewhere where it shouldn't be, so instead of something like -fmarch=arm you're getting -fmarch= arm. Obviously this is just an example because you didn't provide nearly enough information.
One other note: we can't know how your makefiles work but typically makefiles that support a variable like CROSS_COMPILE expect it to be set to just the prefix of the cross-compilation command; in your case it would be CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-. But, your makefiles might be different.
When asking questions, it's best to if you don't immediately jump to a guess about what the answer is. First describe the problem, and that includes showing the error line as well as a few lines before it. For example in this case you're getting an error from g++ so the command line that make printed out showing you how it invoked g++ would have helped greatly.
Once you've given the underlying detail, then if you think you have an idea about what the problem is go ahead and suggest it, and/or ask about it.
If you provide the rule that invokes g++ and/or the output from make showing the g++ command line, then we can help more.
Cheers!
Here's what I think needs to happen:
You need to make sure that your sub-makefiles actually respect the $(ARCH) and $(CROSS_COMPILE) variables. Are they also generated by Premake? If so, is that how it handles cross-compilation? Check the docs.
In my test (below), I found that variables set on the command line are propagated to sub-makes, which makes me think that your sub-makefiles aren't respecting $(ARCH):
Makefile:
a:
$(MAKE) -C z
z/Makefile:
a:
#echo "MAKE=$(MAKE)"
#echo "ARCH=$(ARCH)"
Running make with no arguments:
$ make
make -C z
make[1]: Entering directory `/home/foo/test/z'
MAKE=make
ARCH=
make[1]: Leaving directory `/home/foo/test/z'
Running make ARCH=bar:
$ make ARCH=bar
make -C z
make[1]: Entering directory `/home/foo/z/z'
MAKE=make
ARCH=bar
make[1]: Leaving directory `/home/foo/z/z'
I have Makefile like this:
b:
#echo "b"
a:
#echo "a"
#make b
I want this Makefile to print "a\nb" after i execute 'make a'. It does the
thing, but It also prints "Entering directory" and "Leaving directory":
$ make a
a
make[1]: Entering directory `/home/bessarabov'
b
make[1]: Leaving directory `/home/bessarabov'
Actually that lines doesn't disturb me, but I'm not sure that this is the
correct way of running some targets in the end of other targets.
GNU make has a switch to silence the Entering/Leaving messages: --no-print-directory. using make usually isn't right, you probably want to change it to $(MAKE).
rationale for $(MAKE) versus "make" is given in the GNU make manual here and here