system verilog - implementation of randomize() - random

Question

I have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn't support this function.
I implemented a basic function in a class with the following member:
bit [15:0] data_xi;
bit [15:0] data_xq;
the basic random function:
//function my_randomize
function int my_randomize(int seed);
int temp1, temp2;
temp1 = (($urandom(seed)) + 1);
data_xi = temp1 - 1;
temp2 = (($urandom(seed)) + 1);
data_xq = temp2 - 1;
if(temp1 != 0 || temp2 != 0 )
return 1;
else
return 0;
endfunction: my_randomize
Now I have to change it to static function which suppose to behave like randomize() with constraints.
How can I implement this?

Answer 1

1) To make your function like constraints, you can have inputs to your function to set the range or a modulo.
//function my_randomize
function int my_randomize(int seed, int temp1_min, int temp1_max, int temp2_min, int temp2_max, int temp3_min, int temp3_max);
int temp1, temp2, temp3;
temp1 = $urandom_range(temp1_min, temp1_max);
temp2 = (($urandom(seed)) % (temp2_max+1));
data_xi = temp2 - 1;
temp3 = ((($urandom($urandom(seed))) % temp3_max+1) + temp3_min;
data_xq = temp3 - 1;
if(temp1 != 0 || temp2 != 0 )
return 1;
else
return 0;
endfunction: my_randomize
Ofcourse you can decide how to implement the randomization for temp1, temp2 and temp3. These are some ideas.
2) If you want all classes to access this function, create a base class with the randomize functionality, and then derive all your classes from it. Although you won't have access to the derived class variables in this case, just base-class variables. You can always make this a virtual function to override in your derived class.
3) Note that using the same seed for $urandom/$urandom_range in the same thread will create the same random number.