first, thanks to all.
I ' ve been kind of 3 hours trying to find out whats wrong, I have done a deep research on the internet and I found nothing that worked for me.
I' ve tried a lot of examples which ended the same way; missing separator or nothing to be done.
What could it be?
My .c and .h are called the same way 3enRayaPunteros.c/h
Here's my makefile's code:
Juego: 3enRayaPunteros.o
gcc -o Juego 3enRayaPunteros.o
3enRayaPunteros.o: 3enRayaPunteros.c 3enRayaPunteros.h
gcc -c 3enRayaPunteros.c
Thank you so much:
Try
Juego: 3enRayaPunteros.o
gcc -o $# $+
3enRayaPunteros.o: 3enRayaPunteros.c 3enRayaPunteros.h
gcc -c -o $# $^
You want your executable Juego to depend on a .o file. That object file needs to depends on your source files .c, .h, ....
It's common practice to refer to the target name with $#, refer to all the prerequisites with $+ and refer to the first prerequisite with $^.
Missing seperator usually means you are mixing up spaces and tabs. Make is very fiddly when it comes to this so do NOT use tabs to indent anything but recipes. Nothing to be done means exactly what the message says: there is nothing to be done for what you asked make to do.
Related
I am doing a nasm project, and I need to execute the ej and use as a parameter the ex.asm . I tried searching through GNU how can I pick one by one the parameter. My solution has been writing ex1_ and ex2_, but I want to put those inside the $(ex) dependency, so I don't have to replicate multiple times the same code. Is there any way?
Thank you in advance
The code:
ej = ej1_gen ej2_gen
ex = ex1 ex2
# -----------------------------------------------
all: $(ej) $(ex)
exs: ex1_ ex2_
# -----------------------------------------------
$(ex): exs
nasm -g -o $#.o -f elf32 $#.asm
$(CC) $(FLAGS) -m32 -o $# $#.o alfalib.o
ex1_:
./ej1_gen ex1.asm
ex2_:
./ej2_gen ex2.asm
As I read the question, you have programs or scripts ej1_gen and ej2_jen in the project, serving to generate the wanted assembly sources. They each take the name of the output file as a command-line argument. Parts of this answer would need to be adjusted if that's a misinterpretation.
Rules to describe how to build the assembly files should designate the resulting assembly file(s) as the target. Also, supposing that the code-generator programs are part of the project, they should be designated as prerequisites, since changing those could cause them to produce different outputs. Any configuration files or similar that they read to inform their results should also be named as prerequisites (not shown). That leads to rules something like this:
ex1.asm: ej1_gen
./ej1_gen $#
ex2.asm: ej2_gen
./ej2_gen $#
It sounds like you may be asking for a way to express that via just one rule covering both, but I would not do so in this case. I don't think you get any clearer than the above, even if there are more than two assembly files to generate. It might be different if the same code generator program were being used, with different options, to generate all the assembly files, or perhaps if the generator name could be derived more directly from the target name.
With those rules in place, you can write a generic suffix rule or pattern rule to assemble the resulting files. Since you tag [gnu], I'll assume that a pattern rule is acceptable:
%.o: %.asm
nasm -g -o $# -f elf32 $<
And you can take a similar approach to expressing a link rule:
%: %.o alfalib.o
$(CC) $(FLAGS) -m32 -o $# $^
With that, you should be able to get rid of the ej variable and the exs target, too, leaving
all: $(ex)
as the only other rule (and it should still appear first in the file, as it does now).
Im trying to run this simple makefile commands but get the error - 'Nothing to be done for 'all''
FILES = file1.c file2.c file3.c
all:test
test:
for file in $(FILES);
do
echo $$file;
done
The target test has no dependencies and therefore no reason to be built, which is inherited by the target all. It has instructions, but it should include FILES as its prerequisites. What you're doing appears to be ingredients-first, but test is the target. Working backwards is what make is best at. You may benefit from an article called "Auto-Dependency Generation" which takes the opposite approach (you appear to think like I do.)
test: $(FILES)
Then you could do something like the following:
$(FILES:.o:.c): %.o: %.c
$(CC) -c -o $# $<
The first part is a set of possible targets, the list of objects corresponding to the list of sources, and the second is a specific but nameless object (it will assume the name of the corresponding source.) Later on, the target, e.g. test, can be the name of your executable taking these objects as both dependencies and objects to link statically. For my purposes I typically use shared libraries but this is irrelevant to the question at hand.
Edit: untested, will revise if issues ensue
i have been trying to make a correct makefile for a while now but i keep getting the error "make: *** No rule to make target `all'. Stop."
i have one main program: mpasswdsort.c
and the c file wich is used by mpasswdsort, it comes with a header as well:
list.c and list.h
my makefile:
CC=gcc
CFLAGS=-Wall -pedantic -ansi
all: mpasswdsort
server: mpasswdsort.o list.o
$(CC) mpasswdsort.o list.o -o mpasswdsort
mpasswdsort.o: mpasswdsort.cpp
$(CC) $(CFLAGS) mpasswdsort.cpp
list.o: list.cpp
$(CC) $(CFLAGS) list.cpp
clean:
rm -f server client *.o core
I am unsure if its wrong in the makefile or if the makefil isnt supposed to be a .txt file.
The error message you present indicates that make does not see any rule for building target "all". It is exactly the same diagnostic that GNU make emits when there is no makefile at all. Since the makefile contents you present do contain a rule for target "all", I conclude that make is not seeing them.
That may be because the makefile is in a different directory, because its name is different from the ones make tries by default (Makefile or makefile is conventional; GNU's version of make also checks for GNUmakefile), or because an access-control issue prevents make from reading the file. Since you remark
I am unsure if its wrong in the makefile or if the makefil isnt
supposed to be a .txt file.
, the most likely conclusion is that (at least) the filename is wrong. Makefiles are text files, but text file names don't necessarily end with ".txt". In fact, on Linux and other UNIXes, most of them don't. Makefiles shouldn't have such an extension, though, technically, you can use the -f option to tell make the name of the makefile to use.
For me, quite simply, I was initiating the make init command outside of the target directory that I wished to create the makefile. Hope this helps someone.
I'm using a MAC so renaming the "MakeFile" to "Makefile" did the trick for me.
And one more thing, I got this error after fixing the previous one:
Makefile:3: *** missing separator. Stop.
Replacing the four spaces with tabs solved this problem for me! Simply just delete the space before the commands in your "Makefile" and put a tab behind them.
I recently browsed through a makefile with these lines of code in a OS design course at CMU.
$(TEST_PROGS) tests/verify_test: %: %.o libtraceback.a
$(CC) -o $# $#.o -L. libtraceback.a $(CFLAGS) $(LDFLAGS) $(LIBS) -static
python ./symtabgen.py $#
I don't understand what "%:" could mean here. The TEST_PROGS variable contains list
traceback/traceback_globals.o traceback/traceback.o
traceback/traceback_globals.o traceback/traceback.o are required in making libtraceback.a
I've went so far as to play around with removing %.o. Doing so stopped the TEST_PROGS objects from compiling
Removing %: but keeping %.o gave out several warnings and nothing compiled.
I'm hoping someone could shed some light into the syntax of makefile here. A quick Google search revealed that %: is related to secondary expansion. But in this code that I'm looking at,the special target .SECONDEXPANSION isn't defined.
Please help, this code makes my brains hurt ...
The canoncial place to look is the Make manual.
Anyway, this an example of a static pattern rule. It uses wildcards to specify a relationship between each target and a similarly-named prerequisite.
This is a static pattern.
This is what it means:
Your target is any of the files described by $(TEST_PROGS) or test/verify_test
What you need to build your target is the second part: %.o libtraceback.a
The string that will replace the % symbol is exactly the name of the file that you are trying to build.
So, for example, executing
make test/verify_test
will set % to be "test/verify_test" and it will require test/verify_test.o and libtraceback.a
I am very very new to makefiles. The most complex task I had done before was to include new .h and and .cpp or .c in already designed makefiles.
I have to port the compilation process of a project from Visual Studio to gcc and there is an already made solution for this written by a colleague but he used 4 bash scripts and a makefile to compile the solution.
Instead of doing that I was looking for solutions to make it easier to maintain. My question may be very dumb I admit, but I could not find it anywhere nor I could understand it all properly.
In the target below:
$(OBJECTS): %.o: %.cpp
$(CC) $(CPPFLAGS) -c $< -o $#
I would like to test if the .o being created already exists and rename it to something else. This is necessary because in the project there are several source files that have the same name yet they are different in content.
For example, if the current .cpp being compiled is called file.cpp and the object that will be generated is file.o, the rule should test whether file.o already exists and rename the current file.o to something else.
If you know any good tutorial that explains this, please let me know. I found lots of examples that show how to make tests for the current file being compiled by that rule, but none that would rename the object .o.
Thanks in advance and sorry for any "dumbness" written here. :-)
First of all, you have our deep sympathy.
Make is not really designed to handle such ambiguity, so we'll have to use a kludge. You haven't said what you want to rename the file to, so for now lets say we move file.o to file_save.o.
# This tells Make that these are not real targets, so that it will
# proceed even if file.o already exists.
.PHONY: $(OBJECTS)
$(OBJECTS): %.o: %.cpp
# If file.o exists, move it to file_save.o
#if [ -f $# ]; then mv $# $*_save.o; fi
$(CC) $(CPPFLAGS) -c $< -o $#
Expansion of my comment on the question:
Perhaps you should consider placing object files in the same directory hieryarchy as the source files, to prevent naming conflicts.
So that src/network/client.cpp is compiled to build/obj/network/client.o.
I'm extremely rusty when it comes to makefiles but I believe I solved that by doing something like:
$SRC= src/network/client.cpp src/main.cpp .....
$OBJ= makefile_replace_function($SRC, .o)
$(OBJ) : $(SRC)
compile_instructions
Where you will have to replace makefile_replace_function and compile_instructions to their real equivalents since I have forgotten then...
I realize this might not be very helpful but atleast its an idea to consider.