I'm trying to make my own Makefile for a Fortran code. It looks very alike to another Makefile, which can perfectly work. But unfortunately I can't find out what's wrong by myself. The configuration is described below:
I have a main folder containing sub-folders name src, lib, results, mod, obj. Makefile itself is also in the main folder. I have several fortran sources files in the src folder, say main.f90, subroutine_1.f90, subroutine_2.f90, module_1.f90 and module_2.f90. Subroutine_1 and subroutine_2 are included in module_1, module_2 in also used in module_1. In this case I only need main.f90 and module_*.f90 to be included in my Makefile(if that's not wrong). I also have a static library to be used.
# For WINDOWS
RM := del
PS := $(strip \)
#--------------------- DICTIONARY ---------------------
BUILD_DIR := .
SRC_DIR := $(BUILD_DIR)$(PS)src
LIB_DIR := -L$(BUILD_DIR)$(PS)lib
TAR_DIR := $(BUILD_DIR)$(PS)results
MOD_DIR := $(BUILD_DIR)$(PS)mod
OBJ_DIR := $(BUILD_DIR)$(PS)obj
#------------------ COMPILER AND FLAG ------------------
FC := gfortran
FCFLAGS := -g -c -fbacktrace -fno-align-commons -fbounds-check\
-J"$(MOD_DIR)"
FLFLAGS :=
#------------------- TARGET & SOURCE--------------------
TARGET := $(TAR_DIR)$(PS)main.exe
SRC := $(notdir $(wildcard $(SRC_DIR)$(PS)module_*.f90))\
main.f90
LIB := -lfftw3-3.lib
LDFLAGS := $(LIB_DIR)
OBJ := $(patsubst %.f90, $(OBJ_DIR)$(PS)%.o, $(notdir $(SRC)))
all: $(TARGET)
# Final linking
$(TARGET): $(OBJ)
$(FC) $(FLFLAGS) -o $# $(OBJ) $(LDFLAGS) $(LIB) #line a
$(OBJ_DIR)$(PS)%.o: $(SRC_DIR)$(PS)%.f90
$(FC) $(FCFLAGS) -o $# $< #line b
clean:
-$(RM) -f $(OBJ_DIR)$(PS)*.o
-$(RM) -f $(MOD_DIR)$(PS)*.mod
I got many errors from the make process but I guess they all come from the same place.
$ make
Makefile:line a: warning: overriding recipe for target '.'
Makefile:line b: warning: ignoring old recipe for target '.'
make: Circular . <- . dependency dropped.
make: *** No rule to make target 'src\%.f90', needed by '.'. Stop.
Except from the error, I also have several questions:
How to choose appropriate flags for compiling?
Since module_2 is used in module_1, do I need to compile them in order? In reality I have many modules so I don't think I'm able to specify that one by one...
When do I need to create a dependency .d file? I don't quite know how it works.
Do I need to compile .mod out of .o? For example add a line
%.mod: %.o
Thanks a lot.
Related
I'm fairly new to Makefiles, and I am trying to create one for a C project I am building using gcc.
I am familiar with the error Makefile:<col>: *** missing separator. Stop. It has popped up before when I used spaces instead of tabs to precede rules in the Makefile. I just tried writing a Makefile for this particular project (being sure to use TAB character instead of spaces) and when I run the make command, I get a very nondescript error I do not understand how to fix: src/main.c:7: *** missing separator. Stop
My directory structure looks like this:
- projectfolder/
- Makefile
- bin/
- build/
- inc/
- src/
- main.c
- otherfolder/
- inc/
- common.h
- io.h
- src/
- io.c
main.c, which includes the main function, has the following imports:
#include <stdio.h>
#include <stdlib.h>
#include "common.h"
#include "io.h"
My goal is to make a bunch of .o and .d files from the files in both src/ and inc/ directories and put those into projectfolder/build/, so that they can then be used to make the final executable in projectfolder/bin/
Finally, here is the Makefile that is causing the issue:
# Compiler and linker
CC := gcc
# Target binary
TARGET := the-program
# File extensions
SRCEXT := c
# Directories
TARGETDIR := bin
BUILDDIR := build
SRCDIRS := src /home/myusername/otherfolder/src
INCDIRS := inc /home/myusername/otherfolder/inc
# gcc options
CCFLAGS := -Wall -Wextra -O3
#---------------------------------------------------------------------------------
#DO NOT EDIT BELOW THIS LINE
#---------------------------------------------------------------------------------
vpath %.$(SRCEXT) $(SRCDIRS)
vpath %.h $(INCDIRS)
CCFLAGS += $(addprefix -I,$(INCDIRS)) -MMD -MP
SRC := $(shell find $(SRCDIRS) -name *.$(SRCEXT))
OBJ := $(SRC:$(SRCDIRS)/%.$(SRCEXT)=$(BUILDDIR)/%.o)
DEP := $(OBJ:.o=.d)
TARGET := $(TARGETDIR)/$(TARGET)
# RULE: Default make
all: makedirs $(TARGET) clean
# RULE: Remake
remake: fullclean all
# RULE: Clean
clean:
rm -rf $(BUILDDIR)
# RULE: Full clean (objects and binaries)
fullclean: clean
rm -rf $(TARGETDIR)
# RULE: Make dirs
makedirs:
mkdir -p $(BUILDDIR)
mkdir -p $(TARGETDIR)
# RULE: Link
$(TARGET): $(OBJ)
$(CC) $(OBJ) -o $#
# RULE: Compile
$(OBJ): $(SRC)
$(CC) $(CCFLAGS) -c $< -o $#
# RULE: Non-file targets
.PHONY: all remake clean fullclean makedirs
# include dependencies
-include $(DEP)
What about this file would cause the described error? I am assuming that it is related to the Makefile itself rather than the C code actually contained in src/main.c since this does not appear to be a compilation error, but if I am wrong, let me know and I can change the post.
This error:
src/main.c:7: *** missing separator. Stop
is clearly being printed by make. Since we know the format of these messages is <makefile>:<linenumber>: <error>, we can see that make is trying to parse the file src/main.c as a makefile and obviously this cannot work.
How could make be doing such a thing? The obvious culprit is this line:
-include $(DEP)
If the variable DEP contains the file src/main.c, then make would try to include that as a makefile and parse it. So how is DEP set?
DEP := $(OBJ:.o=.d)
This changes all words in OBJ that end with .o to end with .d. Crucially, it should be noted that this makes no changes to words that do not end in .o. So, if OBJS contained src/main.c, this would pass it through unmodified to DEPS.
So how is OBJ set? Here are the relevant variables:
SRCDIRS := src /home/myusername/otherfolder/src
SRC := $(shell find $(SRCDIRS) -name *.$(SRCEXT))
OBJ := $(SRC:$(SRCDIRS)/%.$(SRCEXT)=$(BUILDDIR)/%.o)
Let's expand this: the SRC variable runs:
find src /home/myusername/otherfolder/src -name *.c
(you really should escape the *, either with backslash or quotes: it's very dangerous how you have this).
Now we'll say that SRC gets the value:
SRC := src/main.c /home/myusername/otherfolder/src/other.c
Now what does OBJ contain?
OBJ := $(SRC:src /home/myusername/otherfolder/src/%.$(SRCEXT)=build/%.o)
This clearly cannot work: you can't put multiple directories into SRCDIRS, but then treat it as if it contained only one word.
The problem is in the line
OBJ := $(SRC:$(SRCDIRS)/%.$(SRCEXT)=$(BUILDDIR)/%.o)
The pattern substitution works only where the pattern matches and leaves all other strings alone.
As a simple demonstration see this makefile (no rules, just variable assignments):
x := foo bar baz
y := $(x:ba%=gu%)
$(info $(x))
$(info $(y))
Output:
foo bar baz
foo gur guz
As you can see, foo still is there, unchanged although it didn't match the pattern ba%.
In your case you are passing an impossible to substitute pattern, the content of $(SRCDIRS), which is the two words: src /home/myusername/otherfolder/src to the substitution call, therefore main.c - which is either src/main.c or /home/myusername/otherfolder/src/main.c remains unchanged in your list, gets inadvertently flushed further into $(DEP) and is finally included as text with your last line -include $(DEP).
As a recommendation I want to point you to VPATH (see manual and here: https://www.cmcrossroads.com/article/basics-vpath-and-vpath), which is the better alternative to indicate the location of your sources to make.
I have to make a XC8 project in Ubuntu terminal with makefile.
The directory structure is like this
Project/lib/GPIO/gpio.c
Project/lib/GPIO/gpio.h
Project/main.c
Project/Makefile
Project/build/lib/GPIO
The makefile is generating intermediate files in the Project directory itself. Actually makefile will goto each location and generates intermediate files for each .c file.
Like this
Project/gpio.d
Project/gpio.p1
Project/gpio.pre
Project/<other files>
But I wanted to generate them in Project/build/lib/GPIO instead.
i.e
Project/build/lib/GPIO/gpio.d
Project/build/lib/GPIO/gpio.p1
Project/build/lib/GPIO/gpio.pre
Project/build/<other files>
Makefile:
CHIP := 18F4580
CC := xc8
INCLUDE_PATH := /opt/microchip/xc8/v2.10/include/
PROG := /usr/share/tinybldlin/tinybldlin.py
PORT := /dev/ttyUSB0
AR := libr
SRC_DIR := $(wildcard *.c)
INC_DIR := $(wildcard *.h)
LIB_DIR := \
. \
lib \
lib/GPIO
BUILD_DIR := \
build/ \
build/lib/GPIO
TARGET := pic${CHIP}
FLASH_REGION := 0-3000
ifeq (${SRCS},)
SRCS := $(foreach libdir, $(LIB_DIR), $(wildcard $(libdir)/*.c))
endif
ifeq (${INCS},)
INCS := $(foreach libdir, $(LIB_DIR), $(wildcard $(libdir)/*.h))
endif
ifeq (${OBJS},)
OBJS := $(SRCS:.c=.obj)
endif
ifeq (${P1},)
OBJS := $(SRCS:.c=.p1)
endif
MIN_CFLAGS := --chip=${CHIP} -I${INCLUDE_PATH} --ROM=${FLASH_REGION}
# The following MSG_CFLAGS controls the compiler messages
MSG_CFLAGS := -Q
# The following OPT_CFLAGS reduces the code size
OPT_CFLAGS := --opt=all
# The following OUT_CFLAGS controls the generated outputs
OUT_CFLAGS := --asmlist --summary=psect,mem -M${TARGET}.map
EXTRA_CFLAGS += ${MSG_CFLAGS} ${OPT_CFLAGS} ${OUT_CFLAGS}
CFLAGS := ${MIN_CFLAGS} ${EXTRA_CFLAGS} -DCOMPILER=${COMPILER}
ARFLAGS := r
${TARGET}.hex: ${OBJS}
${CC} ${CFLAGS} -intel $^ -o$#
${MAKE} xclean
${TARGET}.bin: ${OBJS}
${CC} ${CFLAGS} -bin $^ -o$#
${MAKE} xclean
%.p1: %.c ${INC_DIR}
${CC} ${CPPFLAGS} ${CFLAGS} --pass1 $<
%.obj: %.c ${INC_DIR}
${CC} ${CPPFLAGS} ${CFLAGS} -C $<
%.as: %.c ${INC_DIR}
${CC} ${CPPFLAGS} ${CFLAGS} -S $<
%.lib: %.obj
${AR} ${ARFLAGS} $# $<
The first thing I'll say is that this answer relies on your using GNU make. You don't say for sure that you are but since you're using pattern rules I will assume so. Note that what you want to do is not possible with standard POSIX make (unless you want to write out explicit rules for every target to be built).
You need two things:
Tell your compiler what you want to do
Tell make what you want to do
For #1, by default the compiler will generate the output which is the input file name, minus the extension (e.g. .c) plus a specific extension (e.g. .as). Since your input file is lib/GPIO/gpio.c the compiler generates gpio.as. Most compilers support a -o option which allows you to rename the output: you'll have to check your compiler's documentation if this doesn't work. So, you'd want to write your rule:
%.as: %.c ${INC_DIR}
${CC} ${CPPFLAGS} ${CFLAGS} -S -o $# $<
(etc.). Now when you compile lib/GPIO/gpio.c into lib/GPIO/gpio.as, make will set $# to lib/GPIO/gpio.as and invoke your compiler such that it creates lib/GPIO/gpio.as not gpio.as.
But you wanted to put the output files in a build subdirectory. Now that you've convinced your compiler to write files where make tells it to, you have to tell make where to put the output.
So first, when you generate the output files to be created you have to create them with the correct path:
OBJS := $(SRCS:.c=.p1)
That converts lib/GPIO/gpio.c into lib/GPIO/gpio.p1 which isn't what you want. You need this:
OBJS := $(SRCS:%.c=build/%.p1)
Now, make knows you want to build build/lib/GPIO/gpio.p1 instead. However now you'll get an error because make doesn't know how to create that file. You've told it how to build a %.p1 from %.c, but the % must be an exact text match between the target and prerequisite, and here the target % matches build/lib/GPIO/gpio but there's no build/lib/GPIO/gpio.c so the rule doesn't match. You need to rewrite the rule like this:
build/%.p1: %.c ${INC_DIR}
${CC} ${CPPFLAGS} ${CFLAGS} --pass1 -o $# $<
Now it should work. You might also want to add in a mkdir to ensure the directory exists:
build/%.p1: %.c ${INC_DIR}
#mkdir -p ${#D}
${CC} ${CPPFLAGS} ${CFLAGS} --pass1 -o $# $<
I learning to write makefile. I meet a problem today. My makefile makes the main target successfully. Then I delete the main target and run the "make" command again. But the makefile did not make the main target, just show "make: `main.o' is up to date". I don't know why. Here is my makefile and folder structure:
CXX := g++
FLAGS := -std=c++11
INCLUDE_DIR := $(shell find . -type d)
SOURCE_DIR := $(INCLUDE_DIR)
SOURCE_FILE := $(foreach dir, $(SOURCE_DIR), $(wildcard $(dir)/*.cpp))
OBJECT_FILE := $(SOURCE_FILE:%.cpp=%.o)
-include $(OBJECT_FILE:%.o=%.d)
TARGET := app
all: $(TARGET)
$(TARGET): $(OBJECT_FILE)
$(CXX) $(FLAGS) -o $# $(OBJECT_FILE)
$(OBJECT_FILE): %.o: %.cpp | $(SOURCE_DIR)
$(CXX) $(FLAGS) -c $< -o $# -MD -MF $(#:.o=.d)
./-----main.cpp
|---test
|---func.h
|---func.cpp
Unless you choose a specific target to be built on the command line (via make <target>), make will always choose the first target it sees in the makefile as the default target to be built
Consider these lines in your makefile:
-include $(OBJECT_FILE:%.o=%.d)
TARGET := app
all: $(TARGET)
When nothing is built, there are no .d files so the -include doesn't include anything. Then make finds the target all and uses that as the default.
The second time through the makefile, there are .d files so the -include command includes them. Those files define some targets, the first of which is main.o, and so now that is the first target and built by default.
You should move your -include down to the end of the makefile and ensure that the all target is always the first one built.
Just as an aside, I don't know if it's an artifact of your cut and paste into SO, but many of your lines have extra whitespace at the end. You should be aware that extra whitespace at the end of lines IS SIGNIFICANT in makefiles, in many places. I highly recommend using an editor that will allow you to visualize whitespace and/or automatically strip extra whitespace at the end of lines.
This is in reference to the second response here:
How to generate a Makefile with source in sub-directories using just one makefile
The solution works great for me except for when the make rules are called. They never seem to make any once make-goal is called since the files don't exist in the build directory yet. I tested this by creating empty files in the build directory (just anyting.o) and the make rule is then found
my conclusion is that the % wildcard character is only looking for what is in the directory, and can't find the file so it doesnt make a build rule for it, and thus fails to continue. There are two possible solutions:
1) Find a way to make dummy object files that are overwritten when the compiler actually starts
2) Make make "realize" that the wild card is for anything put into the make-goal function, not what is already in the directory
any pointers?
As far as I know, I am the first one to have this issue
\
MODULES := calibration calibration/settings camera/nikon camera ommon
SRC_DIR := $(addprefix src/, $(MODULES)) src
SDK_INCLUDES := include $(addprefix include/, $(MODULES))
BUILD_DIR := build $(addprefix build/, $(MODULES))
SRC := $(foreach sdir,$(SRC_DIR),$(wildcard $(sdir)/*.cpp))
OBJ := $(patsubst src/%.cpp,build/%.o, $(SRC))
# OpenCV directories, change according to your own installation
CV_INCLUDE_DIR = C:\Users\a0225122\Downloads\opencv\build\include
CV_LIB_DIR = C:\Users\a0225122\Downloads\opencv\bin\lib
CV_LIBS = -llibopencv_core249 \
-llibopencv_highgui249 \
-llibopencv_imgproc249 \
-llibopencv_features2d249 \
-llibopencv_calib3d249
CV_FLAGS = -I$(CV_INCLUDE_DIR) -L$(CV_LIB_DIR) $(CV_LIBS)
HID_API_INCLUDE_DIR := 3rd_party/hidapi-master/hidapi/hid.h
# Compiler instructions
CXXFLAGS = -std=c++11 -Wall -I $(SDK_INCLUDE_DIR) -I $(CV_INCLUDE_DIR) -I $(HID_API_INCLUDE_DIR) -L $(CV_LIB_DIR) $(CV_LIBS) -L $(FLYCAP_LIB_DIR) $(FLYCAP_LIBS)
# Clean up instructions
ifdef SystemRoot #This is windows
CXX = mingw32-g++
RM = del /Q
FixPath = $(subst /,\,$1)
BUILD_DIR := $(call FixPath, $(BUILD_DIR))
SRC_DIR := $(call FixPath, $(SRC_DIR))
SDK_INCLUDES := $(call FixPath, $(SDK_INCLUDES))
SRC := $(call FixPath, $(SRC))
OBJ := $(call FixPath, $(OBJ))
CXXFLAGS := $(call FixPath, $(CV_FLAGS))
define make-goal
$1\%.o: %.cpp
$(CXX) $(CXXFLAGS) -c $$< -o $$#
endef
else #more ifeqs can be added for more OS's but this should be fine
CXX = g++
RM = rm -f
define make-goal
$(1)/%.o: %.cpp
$(CXX) $(CXXFLAGS) -c $$< -o $$#
endef
endif
vpath %.cpp $(SRC_DIR)
SDK_LIBS = lib_core.a
default: SDK.exe
.PHONY: clean
clean:
$(RM) build *.a
#executable generation
SDK.exe: $(SDK_LIBS)
$(CXX) $(CXXFLAGS) $^ -o $#
lib_core.a: checkdirs $(OBJ)
ar rcs lib_core.a $(OBJ)
checkdirs: $(BUILD_DIR)
$(BUILD_DIR):
mkdir $#
#$(OBJ): $(SRC)
# $(CXX) $(CXXFLAGS) -c $^ -o $#
$(foreach bdir,$(BUILD_DIR),$(eval $(call make-goal,$(bdir))))
Your first problem is that you cannot use backslashes in GNU make rules, except in recipes (make just sends the recipe to the shell, it doesn't interpret the recipe except for $). All GNU make targets, prerequisites, etc. must use forward slashes, all the time, even on Windows.
Almost all Windows applications will accept forward-slashes as directory separators properly. For the few that don't, you can use your function FixPath, but you must use it inside the recipe, not in the target or prerequisite lists.
Once you've resolved that issue if you still have problems, post what you have and we'll look.
I'm attempting to put together a makefile that will take source files from a directory (eg. src), compile them into object files in another directory (eg. build), and then take those files and create a static library from them in the main directory.
Here's my effort so far:
LIBNAME := test
LIBNAME := lib$(LIBNAME).a
CC = g++
CFLAGS := -O0 -Wall -g -fPIC
INCLUDE := include
SOURCE := src
BUILD := build
CPPFILES := $(foreach dir, $(SOURCE)/, $(notdir $(wildcard $(SOURCE)/*.cpp)))
OBJFILES := $(addprefix $(BUILD)/, $(CPPFILES:.cpp=.o))
all: $(LIBNAME) $(OBJFILES)
$(LIBNAME): $(OBJFILES)
ar rcs $(LIBNAME) $(OBJFILES)
.cpp.o:
$(CC) $(CFLAGS) -I$(INCLUDE) -c $< -o $#
clean:
rm -rf $(BUILD)
Which gives me this:
make: *** No rule to make target `build/point.o', needed by `libtest.a'. Stop
You seem do be requiring GNU make anyway (foreach function), so rewriting the old-style suffix rule .cpp.o to
$(BUILD)/%.o : $(SOURCE)/%.cpp
should do the trick. You might also try using the VPATH variable or the vpath directive, see the make manual for these.
In general, you might just tackle this problem with automake, which does most of this stuff for you.