reduce the amount of duplicated rules in makefile - makefile

Question

The goal is to specify a build directory where .o and the executable will reside after building the project
currently I've written this Makefile that does this but I have to specify for each object file its directory manually.
PROGNAME = parkingLotApp
CXX = g++
SRC = main.cpp \
parking_car.cpp \
parking_lot.cpp \
shader.cpp \
shader_manager.cpp
OBJS = main.o \
parking_car.o \
parking_lot.o \
shader.o \
shader_manager.o \
BUILDIR = build
CXXFLAGS = -Wall -c -std=c++11
LDFLAGS = -Wall
LIBS = -lGL -lGLEW -lglfw
$(PROGNAME): $(OBJS)
$(CXX) $(BUILDIR)/*.o $(LDFLAGS) $(LIBS) -o $(BUILDIR)/$(PROGNAME)
main.o:
$(CXX) $(CXXFLAGS) $(INCDIR) main.cpp -o $(BUILDIR)/main.o
parking_car.o:
$(CXX) $(CXXFLAGS) $(INCDIR) parking_car.cpp -o $(BUILDIR)/parking_car.o
parking_lot.o:
$(CXX) $(CXXFLAGS) $(INCDIR) parking_lot.cpp -o $(BUILDIR)/parking_lot.o
shader.o:
$(CXX) $(CXXFLAGS) $(INCDIR) shader.cpp -o $(BUILDIR)/shader.o
shader_manager.o:
$(CXX) $(CXXFLAGS) $(INCDIR) shader_manager.cpp -o $(BUILDIR)/shader_manager.o
.PHONY: clean
clean:
rm $(BUILDIR)/*.o $(BUILDIR)/$(PROGNAME)
Again, this works as I expected but I want to get rid of manually specifying directory ($(BUILDIR)/someobject.o) for each .o file
I tried this instead of duplicated lines above
$(OBJS):
$(CXX) $(CXXFLAGS) $(INCDIR) $(SRC) -o $(patsubst %, $(BUILDIR)/%, $(OBJS))
but it gave an error for all build/*.o
saying that
no such file or directory
Why it does not work ?

Answer 1

Your attempt to combine all of the object file rules failed because the compiler did not know that you wanted to compile all of the source files separately.
We start with the object file rules:
main.o:
$(CXX) $(CXXFLAGS) $(INCDIR) main.cpp -o $(BUILDIR)/main.o
...
Then we realize that these rules don't build what they claim to build; this rule claims to build main.o, but it actually builds build/main.o. This will cause trouble later, so we fix it:
$(BUILDIR)/main.o:
$(CXX) $(CXXFLAGS) $(INCDIR) main.cpp -o $(BUILDIR)/main.o
...
Then we notice that we forgot to tell Make about the prerequisite source files-- Make does not know that it should rebuild this target if main.cpp has changed. So we correct that:
$(BUILDIR)/main.o: main.cpp
$(CXX) $(CXXFLAGS) $(INCDIR) main.cpp -o $(BUILDIR)/main.o
...
Then we use automatic variables to reduce the redundancy:
$(BUILDIR)/main.o: main.cpp
$(CXX) $(CXXFLAGS) $(INCDIR) $# -o $#
...
Then we notice that all of these object-file-building rules have exactly the same command, so we combine them into a pattern rule:
$(BUILDIR)/%.o: %.cpp
$(CXX) $(CXXFLAGS) $(INCDIR) $# -o $#
(You could make them into a static pattern rule, but this is enough for one day.)
EDIT:
We must also change the PROGNAME rule to give it the correct name and prerequisites, and use automatic variables:
$(BUILDIR)/$(PROGNAME): $(addprefix $(BUILDIR)/, $(OBJS))
$(CXX) $^ $(LDFLAGS) $(LIBS) -o $#