I've spent many hours and and a ton of paper sketching and I haven't been able to stumble upon anything to get me past this problem.
I can't figure out how to solve this task using PLC ladder language. PLC programme must compute actual flow of water. The gate is moving and the time of gate is set to 5 minutes. In this gate the impulses are counted (with wage for example - wage of 1 m^3). The overall time (the space where the gate can move) is set to 1 hour.
Gate time: for example 5 minutes Overall time: 1 hour Impulse is triggered by me.
Example if we trigger the I1 input - 3 times (one input have wage 1 m^3) in a gate of 5 minutes (5 minutes is 1/12 hour) so 3 * 1m^3 divided by (1/12)h = 36 m^3 / h It gave us actual water flow. I can only use TON timer and I've got 2 binary inputs.
Do you have any idea how to start this?
It's a logger I tried to base on, but now I don't know what to do next.
#include "MT-101.h"
IF FS1_fs MOVE 0, REG2
IF FS1_fs MOVE RTC_Sec, REG2
NE RTC_Sec, REG2, Q1
IF NOT Q1 EXT
MOVE RTC_Sec, REG2
IF NOT I1 EXT
TCPY XREG1, 511, XREG2
MOVE AN1, XREG1
Related
To set the stage, assume a circuit that computes ((a AND b) or c), with the inputs a,b,c changing at the same time, e.g. taken from clocked registers. The delay of the AND gate is negligible, and therefore not modeled at all, but the delay of the OR gate is significant, say 5ns.
The gates are modeled by using an operator and a delayed assignment in two separate processes:
Verilog:
(process 1) temp <= a & b;
(process 2) out <= #5 temp | c;
VHDL:
(process 1) temp <= a and b;
(process 2) out <= temp or c after 5ns;
Now with the right old and new input values, a glitch occurs: (a = 1, b = 1, c = 0) -> (a = 0, b = 1, c = 1). This causes the temp value (output of the AND gate) to become 0 in a delta cycle, and therefore schedule a change of the OR gate to 0 after 5ns. Simultaneously, c becomes 1 and schedules a "change" of the OR gate to 1 (at that time it still is 1).
Now the fun part: Let the inputs change at time 0ns. The change of the OR gate to 1 is scheduled at time 0ns, for time 5ns. The change of the OR gate to 0 is scheduled at time (0ns + 1delta), for 5ns later. A "too simple" model would schedule both for time 5ns and risk that they get
executed in the wrong order, leaving the output of the OR gate at 0 erroneously.
The question now is, how do Verilog and VHDL make sure that the glitch gets resolved correctly? Things they could do it that I can imagine:
allow scheduling for (N cycles + D delta cycles), so the change of the OR gate to 1 gets scheduled for (5ns + 1delta) and is guaranteed to
be executed last.
schedule both for time (5ns), but have the action of scheduling an assignment remove all assignments for the same driver scheduled for the same time
schedule not just the assignment, but the whole computation for time (5ns) and delay the evaluation of gate inputs to that time. However, the answer to this question seems to imply that this is not what happens: Understanding the Verilog Stratified Event Queue
Please note that I am trying to understand the behaviour prescribed by the two languages, not achieve a specific outcome.
For the signal assignments you have shown, Verilog and VHDL both guarantee last write wins. As other have commented, it would have helped to show the complete context of the statements to confirm that is what you intended.
There will be no glitch because the c transition from 0→1 happens before the temp transition from 1→0, separated by a delta cycle. Although you cannot determine the ordering between different concurrent processes, if there is a deterministic ordering within the same process, last write to the same variable wins.
I have to write the VHDL code for the following entity-architecture design:
develop a "machine" with the following signals:
- clock input (100Mhz)
- 4 input lines (1-bit) called: REQ0...REQ3
- 4 output lines (1-bit) called: GRANT0...GRANT3
- a reset signal (input)
The machine checks the input lines on every clock rising edge.
If one input line is "high" (bit 1), it sets an high value on the corresponding GRANT line. The GRANTi line turns low when, on the rising edge of the clock, the corresponding REQi line turns low, or after 8 (module 8 counter) clock cycles.
If more than ones REQi lines are high at the same time, only one GRANTi line can turns high (whatever line GRANTi you want), but can't turns high the line just lowered.
I hope the text is clear. I was not able to figure out the problem.
I've made an I2S transmitter to generate a "sound" out of my FPGA. The next step I would like to do, is create a sine. I've made 16 samples in a LUT. My question is how to implement something like this in VHDL. And also how you load the samples in sequence. Who has tried this already, and could share his knowledge?
I've made a Lookup table with 16 samples:
0 0π
0,382683432 1/16π
0,707106781 1/8π
0,923879533 3/16π
1 1/4π
0,923879533 5/16π
0,707106781 3/8π
0,382683432 7/16π
3,23114E-15 1π
-0,382683432 1 1/16π
-0,707106781 1 1/8π
-0,923879533 1 3/16π
-1 1 1/4π
-0,923879533 1 5/16π
-0,707106781 1 3/8π
-0,382683432 1 7/16π
-6,46228E-15 2π
The simplest solution is to make a ROM which is just a big case statement.
FPGA synthesis tools will map this on ore more LUT's.
Note that for bigger tables only 1/4 of the wave is stored, the other values are derived.
I would like to send out a 24 bit samples, do you also know how to do that with this data (binary!)?
24 bits (signed) mean you have to convert your floating point values to integer values in the range -8388608..8388607. (For symmetry reason you would use -8388608..8388607)
Thus multiply the sine values (which you know are in the range -1..1) with 8388607.
The frequency of the sine depends on how fast (many samples per second) you send.
I have to write a program which selects a random led and lights it up ,however I am having trouble getting the RANDOM function work. I have included the code i have below.
main:
RANDOM w0
w1 = w0// 10+ 1
SELECTCASE w1
Case1:
high b.1
pause 1000
low b.1
Case2:
high b.2
pause 1000
low b.2
ENDSELECT
goto main
Two observations:
1) The code w1 = w0// 10+ 1 sets w1 to a value between 1 and 10, but your select case structure only handles cases 1 and 2. That shouldn't actually be a problem though, as the unhandled values will do nothing - but your code may loop several times before the random sequence produces a 1 or 2. If you want a value between 1 and 2, use w1 = w0 // 2 + 1.
2) As posted your code has some unnecessary colons and lacks some spaces where they should be, at least according to the manual entry for select case. I would try correcting these just in case that's the problem.
Aside from that, can you give more detail on what isn't working? Are you sure that your wiring is correct and a high on those two pins does in fact light the two LEDs? You could try adding sertxd commands within your case structure to confirm whether the code actually reaches each case.
I have a question about this CodeJam problem: Crossing the Road
I implemented dynamic programming solutions and compared results of running my program and first place winner's program on "B-small-practice.in" (click "Solve B-small" to get the file).
My program gives correct answers (the same as first place winner's program) on all 100 test cases except just two: #5 and #6.
Let's look at the case #5:
2 2
1 1 0 10 1 6
10 1 0 1 10 10
There are 4 intersections. My answer is "17". The correct answer is "12". I can't understand how it's possible to get "12"; when I try to do it manually the best I can get is "17". What is the path with cost "12"?
The input can be translated into the following timing for the intersections, where NS indicates the time that the pedestrian is allowed to cross north or south, and EW indicates the time that the pedestrian is allowed to cross east or west.
A -- NS:0 EW:1 NS:2 EW:3
B -- NS:0-4 EW:5 NS:6-15 EW:16 NS:17-26
C -- NS:0-9 EW:10 NS:11-20
D -- EW:0-9 NS:10 EW:11-20
It's easy to see how you could end up with a time of 17, if you cross intersection B in the EW direction at time 16. But the key is that you never have to cross B in the EW direction.
Working backwards from a time of 12, the solution must cross intersection B in the NS direction at time 11. From there it's easy to work backwards to the start.