In a make rule like below. I want to replace to the dot "." character
APPS := example.helloworld example.sample
$(APPS):
#appdir=`echo $#|sed -e s/\./\//`
# do something...
It doesn't work as make does not escape the "\." and "/" characters. Is there an alternative to this?
Note: I can't change app names and I can't use gnu make.
Found a workaround using shell variables. It works like this:
APPS := example.helloworld example.sample
$(APPS):
#dot="\."; \
#slash="\/"; \
appdir=`echo $#|sed -e s/$$dot/$$slash/`
# do something...
Related
Considering that every command is run in its own shell, what is the best way to run a multi-line bash command in a makefile? For example, like this:
for i in `find`
do
all="$all $i"
done
gcc $all
You can use backslash for line continuation. However note that the shell receives the whole command concatenated into a single line, so you also need to terminate some of the lines with a semicolon:
foo:
for i in `find`; \
do \
all="$$all $$i"; \
done; \
gcc $$all
But if you just want to take the whole list returned by the find invocation and pass it to gcc, you actually don't necessarily need a multiline command:
foo:
gcc `find`
Or, using a more shell-conventional $(command) approach (notice the $ escaping though):
foo:
gcc $$(find)
As indicated in the question, every sub-command is run in its own shell. This makes writing non-trivial shell scripts a little bit messy -- but it is possible! The solution is to consolidate your script into what make will consider a single sub-command (a single line).
Tips for writing shell scripts within makefiles:
Escape the script's use of $ by replacing with $$
Convert the script to work as a single line by inserting ; between commands
If you want to write the script on multiple lines, escape end-of-line with \
Optionally start with set -e to match make's provision to abort on sub-command failure
This is totally optional, but you could bracket the script with () or {} to emphasize the cohesiveness of a multiple line sequence -- that this is not a typical makefile command sequence
Here's an example inspired by the OP:
mytarget:
{ \
set -e ;\
msg="header:" ;\
for i in $$(seq 1 3) ; do msg="$$msg pre_$${i}_post" ; done ;\
msg="$$msg :footer" ;\
echo msg=$$msg ;\
}
The ONESHELL directive allows to write multiple line recipes to be executed in the same shell invocation.
all: foo
SOURCE_FILES = $(shell find . -name '*.c')
.ONESHELL:
foo: ${SOURCE_FILES}
FILES=()
for F in $^; do
FILES+=($${F})
done
gcc "$${FILES[#]}" -o $#
There is a drawback though : special prefix characters (‘#’, ‘-’, and ‘+’) are interpreted differently.
https://www.gnu.org/software/make/manual/html_node/One-Shell.html
Of course, the proper way to write a Makefile is to actually document which targets depend on which sources. In the trivial case, the proposed solution will make foo depend on itself, but of course, make is smart enough to drop a circular dependency. But if you add a temporary file to your directory, it will "magically" become part of the dependency chain. Better to create an explicit list of dependencies once and for all, perhaps via a script.
GNU make knows how to run gcc to produce an executable out of a set of .c and .h files, so maybe all you really need amounts to
foo: $(wildcard *.h) $(wildcard *.c)
What's wrong with just invoking the commands?
foo:
echo line1
echo line2
....
And for your second question, you need to escape the $ by using $$ instead, i.e. bash -c '... echo $$a ...'.
EDIT: Your example could be rewritten to a single line script like this:
gcc $(for i in `find`; do echo $i; done)
~/Desktop $ echo */*
unix/junk unix/save unix/xyxxy
I would like to cancel the slash so the shell no longer prints the files of the directories. I've found out that
~/Desktop $ echo *\/*
unix/junk unix/save unix/xyxxy
doesn't work
,while
~/Desktop $ echo *\\/*
*\/*
does the job.
Can someone explain why this is happening?
Actually, what you're trying to cancel here is not the special behavior of the \ character, but rather, the special behavior of the two * characters!
Me, I would use
echo '*/*'
or
echo "*/*"
Or, if you wanted to use \, the best way to do it would be
echo \*/\*
Actually, since there are almost certainly no files or directories named "*", you would usually be able to get away with just
echo \*/*
or
echo */\*
When you wrote
echo *\\/*
you were asking to see all the names of all the files in any subdirectory where the subdirectory name ended in a \. There probably aren't any of those, but if you want to, to see what's going on, try invoking
mkdir x\\
touch x\\/y
touch x\\/z
and then do your
echo *\\/*
again. You should see x\/y x\/z!
A single backslash is used for special sequences like for instance \n . So to insert a real - escaping - backslash, you have to write \\.
If all you want is to print the folders within your Desktop then use echo */
echo *\\/* will print anything withing a folder that ends with \
while echo *\/* will print anything withing any folder as the backslash (\) is not scaped
I didn't make myself clear with the earlier answer. What's happening with the last command
~/Desktop $ echo *\\/*
*\/*
is basically \ is escaping the next \ and *\/* is just getting printed like any other ordinary string like it happens with *something or any other string abc
I have a variable containing list of files separated with string _NEWLINE_. I need to output that variable into a file so that each file is in a separate line. The trick is that it needs to works on FreeBSD and Solaris.
This is what I am trying now:
echo "lib/alarms-1.2/priv/snmp_conf/agent.conf: lib/alarms/priv/snmp_conf/agent.conf_NEWLINE_lib/alarms-1.2/priv/snmp_conf/agent.conf.src: lib/alarms/priv/snmp_conf/agent.conf.src_NEWLINE_lib/alarms-1.2/priv/snmp_conf/community.conf: lib/alarms/priv/snmp_conf/community.conf" | sed 's|_NEWLINE_|\'$'\n|g'
This works on FreeBSD and in shell on Solaris. But when run in GNUmakefile on Solaris I am getting this (notice $ at the end of each line):
lib/alarms-1.2/priv/snmp_conf/agent.conf: lib/alarms/priv/snmp_conf/agent.conf$
lib/alarms-1.2/priv/snmp_conf/agent.conf.src: lib/alarms/priv/snmp_conf/agent.conf.src$
lib/alarms-1.2/priv/snmp_conf/community.conf: lib/alarms/priv/snmp_conf/community.conf$
If I remove \'$' from sed then it works on Solaris but doesn't on FreeBSD. Maybe there is a way of telling which version to use depending on which system the makefile is executed?
EDIT:
Thanks to the solution proposed by bobbogo I created an exemplary makefile that provides the desired outcome and seems to be working on both FreeBSD and Solaris:
one-line := lib/alarms-1.2/priv/snmp_conf/agent.conf: lib/alarms/priv/snmp_conf/agent.conf_NEWLINE_lib/alarms-1.2/\
priv/snmp_conf/agent.conf.src: lib/alarms/priv/snmp_conf/agent.conf.src_NEWLINE_lib/alarms-1.2/priv/snmp_conf/comm\
unity.conf: lib/alarms/priv/snmp_conf/community.conf
many-lines := { echo '$(subst _NEWLINE_,' && echo ',${one-line})'; }
.PHONY: all
all:
$(shell $(many-lines) > test.txt)
If this is GNU make, then do it all in make.
one-line := lib/alarms-1.2/priv/snmp_conf/agent.conf: lib/alarms/priv/snmp_conf/agent.conf_NEWLINE_lib/alarms-1.2/priv/snmp_conf/agent.conf.src: lib/alarms/priv/snmp_conf/agent.conf.src_NEWLINE_lib/alarms-1.2/priv/snmp_conf/community.conf: lib/alarms/priv/snmp_conf/community.conf
define \n
endef
many-lines := $(subst _NEWLINE_,${\n},${one-line})
Now ${many-lines} has just what you want. Annoyingly, it's quite hard to use in shell lines. If you do this:
tgt:
echo '${many-lines}'
make will invoke a separate shell for each line. The first shell invocation will get an un-paired ' and exit with an error.
.ONESHELL:
tgt:
echo '${many-lines}'
will work in an invasive sort of way. The proper fix is to ensure each line of ${many-lines} has valid sh syntax. Some mouthfull like:
echolines = $(subst ${\n},'${\n}echo ',echo '${many-lines}')
.PHONY: aa
aa:
$(call echolines,${many-lines})
Sheesh.
Tried many different solutions, including defining \n as mentioned in this answer: Add a newline in Makefile 'foreach' loop
The real problem is inconsistent implementation of the echo command across platforms, and the fact that by default make invokes shell commands using sh, which itself is quite inflexible.
I found a better way thanks to this answer: "echo -e" when called directly and when called via a shell-script
The better way is to use printf instead of echo
Construct the string with \n instead of _NEWLINE_ to separate parts that go into separate lines in the output file:
some_string = lib/alarms-1.2/priv/snmp_conf/target_params.conf: lib/alarms/priv/snmp_conf/target_params.conf\nlib/alarms-1.2/priv/snmp_conf/community.conf: lib/alarms/priv/snmp_conf/community.conf\n
and then in the makefile print it simply as this:
#printf "$(some_string)" >> $(some_file)
Works on both, FreeBSD and Solaris.
Disclaimer: I have no experience with Solaris or FreeBSD... here goes anyway.
In make, you can use $(patsubst pattern,replacement,text) to substitute a pattern.
try this...
FILENAMES := "lib/alarms-1.2/priv/snmp_conf/agent.conf: lib/alarms/priv/snmp_conf/agent.conf_NEWLINE_lib/alarms-1.2/priv/snmp_conf/agent.conf.src: lib/alarms/priv/snmp_conf/agent.conf.src_NEWLINE_lib/alarms-1.2/priv/snmp_conf/community.conf: lib/alarms/priv/snmp_conf/community.conf"
.PHONY: all
all:
#echo $(patsubst _NEWLINE_,${\n},$(FILENAMES))
As an alternative, I think your first approach will work, if you just double the $ to "escape" it:
sed 's|_NEWLINE_|\'$$'\n|g'
I went through lots of similar posts but none could be applied to mine.
I would like to search and replace using sed in some particular lines in a way that in only matches the first occurrence; lets say I have this part of the script:
processor <- read.table("../mall_all/adpcm/FULL_DB-constprop", header=TRUE, colClasses=c("reassociate"="factor", "scalarrepl"="factor", "inline"="factor", "sccp"="factor", "loop_reduce"="factor"))
processor<-processor[-c(20:40)]
processor$intensity <- processor$int_high - processor$int_low
processor$performance<- processor$perf_high - processor$perf_low
processor<-processor[-c(1:4)]
processor<-processor[,!names(processor) %in% c("constprop")]
I want to keep changing the $constprop variable in
"../mall_all/adpcm/FULL_DB-constprop"
AND
[,!names(processor) %in% c("constprop")]
in a loop that I wrote, the problem is; I want the colClasses parameteres AND the rest of the scripts remains the same while entering the loop (the loop has the compiler options like: reassociate, inline, constprop, etc)
I was wondering why my search and replace didn't work :
set -x
compilerOptionList="constprop dce inline instcombine licm loop_reduce loop_rotate loop_unroll loop_unswitch loop_unswitch mem2reg memcpyopt reassociate scalarrepl sccp simplifycfg "
stringToBeReplaced=constprop
for compilerOption in $compilerOptionList
do
echo "Using compiler option: $compilerOption"
//here you could see the sed scripts
sed -i "1,15 /FULL_DB/,/header/ s/$stringToBeReplaced/$compilerOption/" r.scr
stringToBeReplaced=$compilerOption
make
mv Rplots.pdf Rplots_adpcm_$compilerOption.pdf
echo "DONE! $compilerOption"
done
Thanks all for your time and help ;)
Amir
I'm not sure having rightly understood your need, but maybe someting like
sed -e "
1,15ba;
/FULL_DB/,/header/ba;
bb;
:a;
s/stringToBeReplaced/$compilerOption/;
:b;
" -i r.scr
could do the job.
This line is problematic
sed -i "1,15 /FULL_DB/,/header/ s/$stringToBeReplaced/$compilerOption/" r.scr
It's not a valid sed command syntax. You'll need to enclose part of it in braces like this
sed -i "1,15 { /FULL_DB/,/header/ s/$stringToBeReplaced/$compilerOption/ }" r.scr
But I think a tidier way is to use separate files for input and output of sed, i.e. change that line to
sed "1,15 s/constprop/$compilerOption/" r.scr_tmp >r.scr
You don't need the stringToBeReplaced variable. This way you always substitute "constprop", and don't have to worry that the string to be replaced appears elsewhere in the code.
r.scr_tmp would contain the same code as r.scr except that the constprop part of r.scr_tmpremains unchanged.
Considering that every command is run in its own shell, what is the best way to run a multi-line bash command in a makefile? For example, like this:
for i in `find`
do
all="$all $i"
done
gcc $all
You can use backslash for line continuation. However note that the shell receives the whole command concatenated into a single line, so you also need to terminate some of the lines with a semicolon:
foo:
for i in `find`; \
do \
all="$$all $$i"; \
done; \
gcc $$all
But if you just want to take the whole list returned by the find invocation and pass it to gcc, you actually don't necessarily need a multiline command:
foo:
gcc `find`
Or, using a more shell-conventional $(command) approach (notice the $ escaping though):
foo:
gcc $$(find)
As indicated in the question, every sub-command is run in its own shell. This makes writing non-trivial shell scripts a little bit messy -- but it is possible! The solution is to consolidate your script into what make will consider a single sub-command (a single line).
Tips for writing shell scripts within makefiles:
Escape the script's use of $ by replacing with $$
Convert the script to work as a single line by inserting ; between commands
If you want to write the script on multiple lines, escape end-of-line with \
Optionally start with set -e to match make's provision to abort on sub-command failure
This is totally optional, but you could bracket the script with () or {} to emphasize the cohesiveness of a multiple line sequence -- that this is not a typical makefile command sequence
Here's an example inspired by the OP:
mytarget:
{ \
set -e ;\
msg="header:" ;\
for i in $$(seq 1 3) ; do msg="$$msg pre_$${i}_post" ; done ;\
msg="$$msg :footer" ;\
echo msg=$$msg ;\
}
The ONESHELL directive allows to write multiple line recipes to be executed in the same shell invocation.
all: foo
SOURCE_FILES = $(shell find . -name '*.c')
.ONESHELL:
foo: ${SOURCE_FILES}
FILES=()
for F in $^; do
FILES+=($${F})
done
gcc "$${FILES[#]}" -o $#
There is a drawback though : special prefix characters (‘#’, ‘-’, and ‘+’) are interpreted differently.
https://www.gnu.org/software/make/manual/html_node/One-Shell.html
Of course, the proper way to write a Makefile is to actually document which targets depend on which sources. In the trivial case, the proposed solution will make foo depend on itself, but of course, make is smart enough to drop a circular dependency. But if you add a temporary file to your directory, it will "magically" become part of the dependency chain. Better to create an explicit list of dependencies once and for all, perhaps via a script.
GNU make knows how to run gcc to produce an executable out of a set of .c and .h files, so maybe all you really need amounts to
foo: $(wildcard *.h) $(wildcard *.c)
What's wrong with just invoking the commands?
foo:
echo line1
echo line2
....
And for your second question, you need to escape the $ by using $$ instead, i.e. bash -c '... echo $$a ...'.
EDIT: Your example could be rewritten to a single line script like this:
gcc $(for i in `find`; do echo $i; done)