Refilling Ram vhdl - vhdl

Question

After writing to each address of Ram and then reading every address of Ram, how would I reinitialize the Ram so that when I write to it again a second time it starts off as if it were the first time writing to it or in other words a clean slate.
Breakdown:
1) write to RAM
2) read from Ram
3) set all ram values back to 0? or can I just go ahead and provide address = 0 begin writing from 0-23 again?
Here is my Ram:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Ram is
Port(
clk : in std_logic;
address : in std_logic_vector(4 downto 0);
write_en : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0)
);
end Ram;
architecture Behavioral of Ram is
type ram_type is array(0 to 23) of std_logic_vector(15 downto 0);
signal Memory : ram_type;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(write_en = '1') then
Memory(to_integer(unsigned(address))) <= data_in;
end if;
data_out <= Memory(to_integer(unsigned(address)));
end if;
end process;
end behavioral;

Answer 1

If you are intending to infer BRAMs in your device it cannot be reset. reset BRAMs is done as part of device configuration. You can always write zeroes (or whetever your initial state is back to the Memory to reinitialize)
However, if you don't care whether it will be synthesized into BRAMs I think the most clean way of doing this is adding a reset port to your system and change your process to take the reset into account. When you want to reset the memory you apply a reset at the input port.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Ram is
Port(
clk : in std_logic;
rstn : in std_logic;
address : in std_logic_vector(4 downto 0);
write_en : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0)
);
end Ram;
architecture Behavioral of Ram is
type ram_type is array(0 to 23) of std_logic_vector(15 downto 0);
signal Memory : ram_type;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(rstn ='0') then
Memory <= (OTHERS => (OTHERS => '0'));
elsif(write_en = '1') then
Memory(to_integer(unsigned(address))) <= data_in;
end if;
data_out <= Memory(to_integer(unsigned(address)));
end if;
end process;
end behavioral;
An additional remark on your code example. If you intend to infer BRAMs your code is "read-before-write". This will result in slower BRAM performance according to WP231 (https://www.xilinx.com/support/documentation/white_papers/wp231.pdf)