I wrote a simple full adder which uses 2 half adders and an OR gate. The VHDL code is pretty simple
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port( x: in std_logic;
y: in std_logic;
s: out std_logic;
c: out std_logic);
end;
architecture x of ha is
begin
s <= x xor y;
c <= x and y;
end;
and
library ieee;
use ieee.std_logic_1164.all;
entity fa is
port( a: in std_logic; b: in std_logic; cin: in std_logic;
sum: out std_logic; cout: out std_logic);
end;
architecture y of fa is
component ha port( x: in std_logic; y: in std_logic;
s: out std_logic; c: out std_logic);
end component;
signal im1, im2, im3: std_logic;
begin
ha1: ha port map( x=>a, y=>b, s=>im1, c=>im2 );
ha2: ha port map( x=>im1, y=>cin, s=>sum, c=>im3 );
cout <= im3 or im2;
end;
The output of the synthesizer however shows there are two XOR gates. Where are the OR gate and others for half adder?
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Xors : 2
1-bit xor2 : 2
=========================================================================
Also, the RTL schematic of the FA is correct, however, the RTL schematic of the half adder is weird! The y port is not present and there is data[1:0]. What does that mean?
FA:
HA:
I've seen the Vivado synthesizer leave stuff off of the macro statistics regularly. Macro reports aren't really meaningful for an FPGA design because all your logic is really going to be mapped into LUTs. In this case it looks like your basic and/or gates aren't considered to be macros, but an XOR is (as indicated by it being a box in the schematic instead of a logic symbol).
As far as your half adder schematic, the tools have combined your two single bit input ports into a two bit bus. The triangles before the and gate are taps on that bus to pull one of the two bits out. It's just another way to represent the same thing.
Related
I am trying to connect the output of an entity to the input of another entity.
Eventually connect a third entity will be connected,but i want to understand the process of connecting two entity's together.
Do I use a port map? If I do, are they added to both architectures of the different entity's to link them?
I know it wont be as simple as below:
link: transmitter port map (output_e1=>input_e2);
I have tried this but an error returns using ModelSim pointing at components declarations!
update:
ENTITY transmitter is
port(
transmission : out STD_LOGIC_VECTOR (31 downto 0)
);
end transmitter;
architecture Behavioral of transmitter is
end Behavioral;
Entity receiver is
PORT(
rxi:in signed (7 downto 0)
end receiver;
architecture Behavioral of receiver is
end Behavioral;
The above code does not include all the instructions and commands. My program works, but i have two entity and wish to link them as they would be in a communications system.
See the following example, a full adder circuit done using two half adders. You can see how the first half adder output is connected as the input of 2nd half adder.
--top module(full adder) entity declaration
entity fulladder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end fulladder;
--top module architecture declaration.
architecture behavior of fulladder is
--sub-module(half adder) is declared as a component before the keyword "begin".
component halfadder
port(
a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end component;
--All the signals are declared here,which are not a part of the top module.
--These are temporary signals like 'wire' in Verilog.
signal s1,c1,c2 : std_logic:='0';
begin
--instantiate and do port map for the first half adder.
HA1 : halfadder port map (
a => a,
b => b,
sum => s1,
carry => c1
);
--instantiate and do port map for the second half adder.
HA2 : halfadder port map (
a => s1,
b => cin,
sum => sum,
carry => c2
);
carry <= c1 or c2; --final carry calculation
end;
See this link for explanation.
I tried to simulate a TFF using Xilinx ISE web pack and ModelSim using following block diagram and structural Code was written using VHDL. But I am unable to get the correct waveform. Due to the T-flip flop is sequential circuit, first I gave the output value as 1 or 0 for one output (Q) to start to the process.
T flip flop truth table and block diagram
simulation waveform
code for AND gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
W : in STD_LOGIC;
Z : out STD_LOGIC);
end AND_GATE;
architecture Behavioral of AND_GATE is
begin
Z <= X AND Y AND W;
end Behavioral;
code for NOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end NOR_GATE;
architecture Behavioral of NOR_GATE is
begin
c <= A NOR B;
end Behavioral;
code for T-FF:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF_2 is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : inout STD_LOGIC;
s : inout STD_LOGIC);
end TFF_2;
architecture STRUCTURAL of TFF_2 is
--declare components being used in T -FF
component TFF is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
component NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end component;
component AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
W : in STD_LOGIC;
Z : out STD_LOGIC);
end component;
--declare signals
signal S1, S2 : STD_LOGIC;
begin
C1 : AND_GATE port map (Q, T, CLK, S1);
C2 : AND_GATE port map (S, T, CLK, S2);
C3 : NOR_GATE port map (S1, S, Q);
C4 : NOR_GATE port map (S2, Q, S);
end STRUCTURAL;
These files synthesized without any errors but in the simulation expected output was not given.
There are a few suggestions I have.
There are non initialised variables. Add := '0'; at the end of the declarations. Simulation might show "X" or unknown. The Synthesised design will work OK, being the hardware will go to one or zero, but simulators need to be directed.
Some of your output variables have feedback into inputs. The design is asynchronous, being that you are not using a clock of some description to time the iterations. Consider using a process and something like if rising_edge(clk)
in reference to this post How to write to two output ports from inside architecture in VHDL? I made a VHDL module using the same concept as decribed in one of its answers.
His code:
entity HIER is
port (
IN1 : in bit;
OUT1, OUT2 : out bit);
end hier;
architecture HIER_IMPL of HIER is
signal temp : bit;
component BUF1 is
port (a : in bit; o : out bit);
end component;
begin
BUF2 : BUF1 port map (a => IN1, o => temp);
OUT1 <= temp;
OUT2 <= temp;
end HIER_IMPL;
His generated RTL(using xilinx 9.1i)
I made a D flip flop using the same concept of signal to drive output ports
my code:
entity dfff is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
end dfff;
architecture Behavioral of dfff is
component nand_2 is
port(A:in std_logic;
B:in std_logic;
C:out std_logic);
end component;
component not_1 is
port(A:in std_logic;
B:out std_logic);
end component;
signal Z : std_logic_vector(4 downto 0);
begin
n1 : not_1 port map (D,z(0));
n2 : nand_2 port map(D,clk,z(1));
n3 : nand_2 port map(z(0),clk,z(2));
n4 : nand_2 port map(z(1),z(3),z(4));
n5 : nand_2 port map(z(2),z(4),z(3));
Q<=z(4);
Qbar<=z(3);
end Behavioral;
my generated RTL(using xilinx 9.1i):
Now MY question is that why My output ports Q and Qbar not visible in the RTL while his OUT1 and OUT2 are?
I am a beginner in this field.
Works fine in ISE14.4. I remember old versions of RTL Viewer being practically unusable.
When I first started writing VHDL I also tried writing a FF in discrete gates, AFAIR it didn't go too well.
You should be writing to your platform (in this case probably some Xilinx chip), knowing what it is and does.
This will also help you when you get on in your training, FPGAs and CPLDs are not great arrays of AND and OR gates, they are great arrays of lookup tables, so the chance of an implementation of a FF in an FPGA turning out well is slim to none.
Regarding your actual question, I'd first make sure I actually have my outputs set to go somewhere. The synthesizer tries very hard not to include superfluous circuitry, so if your result doesn't end in anything, it might get optimized away (even though that should surely also optimize away the circuitry that you did get).
Also as mentioned, try updating your tools, 14.7 is a far stretch newer than 9.1 and that is even from October 2013.
I do not how to write the truth table of this question so I can not do this question, can anyone help me understand what this question let us do? Thank you very much.
An incrementer is a combinational circuit that adds ONE to an input unsigned integer (X). The output unsigned integer (Y) has the same number of bits as the input. There is no output carry, an input string of all ‘1’s increments to all ‘0’s.
a) Write the Full-Adder Equations with inputs A0 , B0 and C0 . (aka Cin)
b) substitute with A0 = X0 , B0 = ‘0’ and C0 = ‘1 and then simplify.
c) Write the Full-Adder Equations with inputs Ai , Bi and Ci.
d) substitute with Ai = Xi , and Bi = ‘0’ and then simplify.
e) Consider a 6-bit Ripple-Adder that has A = X, B = 0 and Cin = ‘1’. Clearly this would be an incrementer. Draw a Structural Diagram of a 6-bit incrementer using the simplified circuits that you have derived in (b) and (d). (Label all instances and signals.)
VHDL can be used to model the time delay of individual gates. Please refer to your lecture notes for the BNF syntax of signal assignment. The delay format is used by simulators but is ignored by synthesizers. Use the following statements to code 2-input gates and inverters.
Code 2-input AND gates using statements with 4 ns delays,Y <= A and B after 4 ns;
Code 2-input XOR gates using the statements with 4 ns delays,Y <= A xor B after 4 ns;
Code inverters using the statements with 1 ns delays,Y <= not A after 1 ns;
Make a new directory called PLA03 and then start a new ModelSim project called PLA03.Always put Entity/Architectures in their own source files and use the Entity name as the filename.
f) Write an Entity/Architecture for your simplified circuit in (b). Name the Entity IncStage0
g) Write an Entity/Architecture for your simplified circuit in (d). Name the Entity IncStageI
h) Write an Entity named Inc6 and a Structural Architecture for your 6-bit Incrementer in (e). Remember to declare the inputs and outputs as unsigned.
library ieee;
use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity IncStage0 is
port(
X:in unsigned;
S: out unsigned;
Cout: out unsigned);
End Entity IncStage0;
Architecture behaviour of IncStage0 is
Begin
S <= not X after 4 ns;
Cout <= X;
End Architecture behaviour;
library ieee;
use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity IncStageI is
port(
X:in unsigned;
Cin: in unsigned;
S: out unsigned;
Cout:out unsigned);
End Entity IncStageI;
Architecture stageI of IncStageI is
Begin
S <= X xor Cin after 4 ns;
Cout <= X and Cin after 4 ns;
End Architecture stageI;
library ieee;
use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity Inc6 is
port(
X:in unsigned (5 downto 0);
Y:out unsigned (5 downto 0));
End Entity Inc6;
Architecture behaviour of Inc6 is
signal C:unsigned (5 downto 0);
Component IncStage0
port(
X:in unsigned;
S: out unsigned;
Cout: out unsigned);
End Component ;
Component IncStageI
port(
X:in unsigned;
Cin: in unsigned;
S: out unsigned;
Cout:out unsigned);
End Component;
Begin
I0: IncStage0
port map(X=>X, S=>Y, Cout=>C);
I1: IncStageI
port map(X=>X, S=>Y, Cout=>C,Cin=>C);
I2: IncStageI
port map(X=>X, S=>Y, Cout=>C,Cin=>C);
I3: IncStageI
port map(X=>X, S=>Y, Cout=>C,Cin=>C);
I4: IncStageI
port map(X=>X, S=>Y, Cout=>C,Cin=>C);
I5: IncStageI
port map(X=>X, S=>Y, Cout=>C,Cin=>C);
End Architecture behaviour;
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity TBInc6 is
End Entity TBInc6;
Architecture rtl of TBInc6 is
signal tbX,tbY: unsigned(5 downto 0);
Begin
DUT: Entity work.Inc6 port map(X => tbX, Y => tbY);
Main: Process
Begin
for i in 0 to 63 loop
tbX <= to_unsigned(i,6);
wait for 30 ns;
end loop;
Wait;
End Process Main;
End Architecture rtl;
After fixing the delay in incStage0 for the NOT (should be 1 ns, not 4 ns),and changing the unconstrained subtype indications for type unsigned to type std_logic (incStage0, incStageI and their component declarations), as well as restoring the indexes for I0 through I5 you removed in your questions 5th edit and then you get:
Which looks correct compared to your instructor's supplied waveform.
Note it's hard to hit a moving target, every time you change your question the answer changes. A good indication you should be asking separate questions.
You could modify inc6 to declare signal C as:
architecture behaviour of Inc6 is
signal C:unsigned (4 downto 0);
component IncStage0
port(
X:in std_logic;
S: out std_logic;
Cout: out std_logic);
end component ;
And change the I5 instantiation:
I5: IncStageI
port map(X=>X(5), S=>Y(5), Cout=> open, Cin=>C(4));
Because you're using name association in the interface list you could simply:
I5: IncStageI
port map(X=>X(5), S=>Y(5),Cin=>C(4));
leave off mention of the carry out.
addendum
Is that means I should change every type unsigned to std_logic or
std_logic_vector?But if I try to change everything to std_logic, it
says no feasible entries for to_unsigned which is in part h code, how
to fix that?
No. unsigned is an array type. From package numeric_std (-2008):
type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype UNSIGNED is (resolved) UNRESOLVED_UNSIGNED;
-1987, -1993, -2002:
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
While in package std_logic_1164 (-2008):
subtype STD_LOGIC is resolved STD_ULOGIC;
-1987, -1993, -2002:
SUBTYPE std_logic IS resolved std_ulogic;
In all revisions of the VHDL standard the base type of std_logic is std_ulogic, which is also the base type of the element type of the array type unsigned.
This means you can connect elements of an unsigned (representing bits) to std_logic signals, including ports. The element base type of both is std_ulogic which is a multi value representation of a bit providing both weak and strong logic level forcing and meta values representing the value of a bit:
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
(Also see IEEE Std 1076-2008, 16.8.2.2 The STD_LOGIC_1164 values - "The logical values '1', 'H', '0', and 'L' of type STD_ULOGIC are interpreted as representing one of two logic levels, where each logic level represents one of two distinct voltage ranges in the circuit to be synthesized.", the one of two logical values, a bit).
As you have undoubtedly discovered you can't connect an array type to a scalar type. incStage0 (I0) and inStageI (I1, I2, I3, I4 and I5) represent bits:
h) Write an Entity named Inc6 and a Structural Architecture for your 6-bit Incrementer in (e). Remember to declare the inputs and outputs as unsigned.
In the code snippets showing the use of an open for an actual on I5 the declaration for C is shown as unsigned and I5 is shown using indexed names (elements on an array object). In addition to declaring the bit slice elements of inc6 as std_logic:
entity IncStage0 is
port(
X:in std_logic;
S: out std_logic;
Cout: out std_logic);
Entity IncStageI is
port(
X:in std_logic;
Cin: in std_logic;
S: out std_logic;
Cout:out std_logic);
component IncStage0
port(
X:in std_logic;
S: out std_logic;
Cout: out std_logic);
end component ;
component IncStageI
port(
X:in std_logic;
Cin: in std_logic;
S: out std_logic;
Cout:out std_logic);
end component;
You want unsigned array values in inc6:
entity Inc6 is
port(
X:in unsigned (5 downto 0);
Y:out unsigned (5 downto 0));
architecture behaviour of Inc6 is
signal C: unsigned (4 downto 0);
And indexed array elements as actuals connected to scalar formals:
begin
I0: IncStage0
port map(X=>X(0), S=>Y(0), Cout=>C(0));
I1: IncStageI
port map(X=>X(1), S=>Y(1), Cout=>C(1),Cin=>C(0));
I2: IncStageI
port map(X=>X(2), S=>Y(2), Cout=>C(2),Cin=>C(1));
I3: IncStageI
port map(X=>X(3), S=>Y(3), Cout=>C(3),Cin=>C(2));
I4: IncStageI
port map(X=>X(4), S=>Y(4), Cout=>C(4),Cin=>C(3));
I5: IncStageI
port map(X=>X(5), S=>Y(5), Cout=> open,Cin=>C(4));
And this leaves TBinc6 as you originally displayed it using unsigned and to_unsigned without error.
And don't forget to change the time specification for delay in incStage0:
architecture behaviour of IncStage0 is
begin
S <= not X after 1 ns;
After which you can generate a wave form that shows identically to the exercise handout.
You've had more that 99 percent of the answer before running into the difference between array type and scalar types and their values. The circumlocution giving you snippets allows students taking the course to claim their work is their own. Learning and understanding, instead of simply copying.
What the question seems to be getting at, is that while you can use a general purpose adder (A + B + carry) to perform an increment, there are certain simplifications if you only need (A + 1) or (A + carry).
It appears to assume you have already been taught basic digital logic, gates, half adders and full adders. If not, this information is easily found.
So start by drawing out the "Full Adder" circuit for each bit. In Step (e), show what the simplifications are (at the gate level) when you simplify a 6 bit adder from (A + B + carry) to (A + carry).
The remaining steps will let you see if the simplified circuit is actually any faster. Looks like a good exercise in using the tools to do something really basic.
library ieee;
use ieee.std_logic_1164.all;
entity ccou is
port(clk2 : in bit;
qc: out bit_vector(3 downto 0);
qnc: out bit_vector(3 downto 0));
end entity;
architecture a_ccou of ccou is
component dfff
port(d,clk1:in bit;
qd,qnd:out bit);
end component;
signal tqc,tqnc: bit_vector(3 downto 0);
begin
g1 : dfff port map(tqnc(3),clk2,tqc(0),tqnc(0));
g2 : dfff port map(tqc(0),clk2,tqc(1),tqnc(1));
g3 : dfff port map(tqc(1),clk2,tqc(2),tqnc(2));
g4 : dfff port map(tqc(2),clk2,tqc(3),tqnc(3));
qc(3 downto 0) <= tqc(3 downto 0);
qnc(3 downto 0) <= tqnc(3 downto 0);
end architecture;
I used structural modelling to design a ring counter, with d flip flop as component. The problem is the program goes to infinite loop. I tried replacing tqnc(3) with '1' or '0' the program runs for finite time but wrong output. Whats the problem and help me rectify it.
and the code for sr flip flop is
library ieee;
use ieee.std_logic_1164.all;
entity srfff is
port(s,r,clk: in bit;
q,qn:out bit);
end srfff;
architecture a_srff of srfff is
component nnand
port(a,b:in bit;
c:inout bit);
end component;
signal ts,tr : bit;
signal tq,tqn: bit;
begin
g1 : nnand port map(s,clk,ts);
g2 : nnand port map(r,clk,tr);
g3 : nnand port map(ts,tqn,tq);
g4 : nnand port map(tr,tq,tqn);
q <= tq;
qn <=tqn;
end a_srff;
This isn't necessarily the final answer. You haven't supplied enough information with your question to determine whether your oscillation is caused by one or both of two possible causes.
I had made changes to your originally supplied code:
entity dfff is
port (
d,clk1: in bit;
qd,qnd: inout bit
);
end entity;
architecture foo of dfff is
begin
process (clk1)
begin
if clk1'event and clk1 = '1' then
qd <= d;
qnd <= not d;
end if;
end process;
end architecture;
-- library ieee;
-- use ieee.std_logic_1164.all;
entity ccou is
port (
clk2: in bit;
qa,qb,qc: out bit; -- inout
cqd: out bit; -- inout
qna,qnb,qnc: out bit; --inout
cqnd: out bit -- inout bit := '1' -- ); -- inout
);
end entity;
architecture a_ccou of ccou is
component dfff
port (
d,clk1: in bit;
qd,qnd: inout bit
);
end component;
-- signal ta: bit;
signal iqa, iqb, iqc, icqd: bit;
signal iqna, iqnb, iqnc, icqnd: bit;
begin
qa <= iqa;
qb <= iqb;
qc <= iqc;
cqd <= icqd;
qna <= iqna;
qnb <= iqnb;
qnc <= iqnc;
cqnd <= icqnd;
g1: dfff port map (icqnd, clk2, iqa, iqna);
g2: dfff port map (iqa, clk2, iqb, iqnb);
g3: dfff port map (iqb, clk2, iqc, iqnc);
g4: dfff port map (iqc, clk2, icqd, icqnd);
end architecture;
entity ccou_tb is
end entity;
architecture foo of ccou_tb is
signal clk2: bit;
signal qa, qb, qc, cqd, qna, qnb, qnc, cqnd: bit;
begin
CLOCK:
process
begin
wait for 10 ns;
clk2 <= not clk2;
end process;
DUT:
entity work.ccou
port map (
clk2 => clk2,
qa => qa,
qb => qb,
qc => qc,
cqd => cqd,
qna => qna,
qnb => qnb,
qnc => qnc,
cqnd => cqnd
);
end architecture;
The changes provided mode out on ccou, adding internal signals, a behavioral model of the dfff flip flop and, a testbench.
That produced:
(clickable)
This is pretty much telling us you have a problem with your dfff flip flop entity/architecture. Note the behavioral dfff model uses an edge clock.
Note your added chalkboard drawing image matches
from the Microarchitecture of Pipelined and Superscalar Computers, 1999 by Amos R. Omandi. And represents a D Latch, not an edge sensitive flip flop.
S R latch feedback oscillation
If your dfff is indeed based on your chalkboard representation one source of oscillation can be remedied by unbalancing the Q BAR to S and Q to R delays on the R S latch or by using a consensus term in an Earle latch.
Essentially when clk1 is false in your dfff implementation SR latch might oscillate because the feed back inputs have events at the same time.
The Earle latch:
uses a consensus term (the middle AND gate) to dampen S R latch oscillation, keeping the output high when the input is high and represents a real world solution that happens to lend itself to simulation.
In device physics we also have the ability to unbalance delays be trimming trace capacitance or transistor size.
Here the S R latch feedback oscillation is a modelling shortcoming that is useful for teaching real design issues.
Enabled Ring delay plus inversion
Unfortunately the ring counter implemented with 'transparent' latches is also susceptible to an oscillation when clk1 (the enable) is true and the ring feedback (g4 qnd output to g1 d input) provides inversion.
We used to call this a striking oscillator, a gated relaxation oscillator.
Fixing the ring feedback oscillation requires using an edge sensitive flip flop or non-overlapping clocks between successive flip flops, preventing a less than 4 clock delay around ring.
See the Wikipedia Master–slave edge-triggered D flip-flop.
A master slave flip flop is implemented with two successive D latches one operating off one phase of the clock (as an enable) and the other off the opposite phase.
These can have requirements for unbalanced feedback delay in the S R latches. The gate level representation shown provides that, plus there are other representations that minimize gate delays.
About now you might get the idea this is a hardware design issue.