VHDL error "Process clocking is too complex." - vhdl

Question

Hello everyone I recently started coding in VHDL(code here is of T flip flop) and I'm having an error which says "Process clocking is too complex", and this is with the first code attached below and surprisingly I the solution too. But I don't know how it worked, code without error is Second code. I googled about the error for half hour but couldn't find the satisfying reason. Please help.
First code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY t_ff IS
PORT(t,clk,rst:IN STD_LOGIC;
q,q_bar:OUT STD_LOGIC);
END t_ff;
ARCHITECTURE t_ff OF t_ff IS
SIGNAL temp: STD_LOGIC;
BEGIN
PROCESS(clk,rst)
BEGIN
IF(clk='1' AND clk'event)THEN
IF(t='1')THEN temp<= NOT temp;
END IF;
ELSIF(rst='1')THEN temp<='0';
END IF;
q<= temp;
q_bar<= NOT temp;
END PROCESS;
END t_ff;
Second code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY t_ff IS
PORT(t,clk,rst:IN STD_LOGIC;
q,q_bar:OUT STD_LOGIC);
END t_ff;
ARCHITECTURE t_ff OF t_ff IS
SIGNAL temp: STD_LOGIC;
BEGIN
PROCESS(clk,rst)
BEGIN
IF(rst='1')THEN temp<='0';
ELSIF(clk='1' AND clk'event)THEN
IF(t='1')THEN temp<= NOT temp;
END IF;
END IF;
q<= temp;
q_bar<= NOT temp;
END PROCESS;
END t_ff;

Answer 1

The reason is quite simple. But first we need to change your code:
Neither version describes the behaviour of a T flip-flop; both describe the behaviour of at least 2, if not 3 flip-flops. This is because
every signal assignment in a clocked process infers a flip-flop
There are 3 signal assignments in each process - to temp, q and q_bar - so you will get 3 flip-flops (though 1 is redundant and so may be optimised away by your synthesiser). So, first, if you want to guarantee that you only have one flip-flop, you need to rewrite each process so that there is only one signal assignment contained within it.
There's no point in re-writing the first process, because it's wrong for other reasons - see later. The second process should be rewritten to something like this:
PROCESS(clk,rst)
BEGIN
IF (rst='1') THEN temp<='0';
ELSIF (clk='1' AND clk'event) THEN
IF (t='1') THEN temp <= NOT temp;
END IF;
END IF;
END PROCESS;
q <= temp;
q_bar <= NOT temp;
In other words, you need to move the assignments to q and q_bar outside the process. This new version of your second version describes the behaviour of a T-type flip-flop with an asynchronous reset:
if the reset is asserted then reset the flip-flop; otherwise, if the T
input is asserted at the rising edge of the clock, then invert the
flip-flop
Had I rewritten your first version, it would describe the behaviour of some electronic component that doesn't exist, so it would not be able to be synthesised. There is no such flip-flop with this behaviour:
if the T
input is asserted at the rising edge of the clock, then invert the
flip-flop; otherwise, if the reset is asserted then reset the flip-flop
You could have described a T type flip-flop with a synchronous reset:
at the rising edge of the clock: if the reset is asserted then reset
the flip-flop, otherwise, if the T input is asserted at the rising
edge of the clock, then invert the flip-flop
like this
PROCESS(clk)
BEGIN
IF (clk='1' AND clk'event) THEN
IF (rst='1') THEN temp<='0';
ELSIF (t='1') THEN temp <= NOT temp;
END IF;
END IF;
END PROCESS;
q <= temp;
q_bar <= NOT temp;
Finally, you are using a rather old-fashioned coding style. I would recommend the use of the rising_edge function. Also your brackets are redundant. An experienced VHDL code would write your second version like this:
PROCESS(clk,rst)
BEGIN
IF rst='1' THEN temp<='0';
ELSIF rising_edge(clk) THEN
IF t='1' THEN temp<= NOT temp;
END IF;
END IF;
END PROCESS;
q <= temp;
q_bar <= NOT temp;