Error in to_integer - vhdl

Question

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_bit.ALL;
use ieee.numeric_std.ALL;
entity multiplexer is
port (A,B: in std_logic_vector (7 downto 0);
CI: in std_logic;
CO: out std_logic;
ANS: out std_logic_vector (7 downto 0);
OP: in std_logic_vector(1 downto 0);
EN: in std_logic);
end multiplexer;
architecture archi of multiplexer is
signal tmp: std_logic_vector (8 downto 0);
begin
process (EN) begin
if (EN = '1') Then
case OP is
when "00" =>
tmp <= std_logic_vector((TO_INTEGER(A)+TO_INTEGER(B)+TO_INTEGER (CI)),9);
ANS<= tmp(7 downto 0);
CO <= tmp(8);
when "01" =>
tmp <= std_logic_vector((to_integer(A)-to_integer(B)+to_integer (CI)),9);
ANS<= tmp(7 downto 0);
CO <= tmp(8);
when others => NULL;
end case;
else
NULL;
end if;
end process;
end archi;
The errors are coming in the To_integer part. I donot know what I am doing wring over here? Also previously I had used the numeric_arith and numeric_unsigned.all and then the subprograms were conv_integer the program compiled but there were no output in the ANS and CO areas. They were defined as undefined. I am attaching the wave output for reference. Please help.
Previous wave output

Answer 1

The issue appears to be having use clauses containing references to both package numeric_std and numeric_bit.
See IEEE 1076-2008 12.4 Use clauses, para 8:
In order to determine which declarations are made directly visible at a given place by use clauses, consider the set of declarations identified by all use clauses whose scopes enclose this place. Any declaration in this set is a potentially visible declaration. A potentially visible declaration is actually made directly visible except in the following three cases:
a) A potentially visible declaration is not made directly visible if the place considered is within the immediate scope of a homograph of the declaration.
b) If two potentially visible declarations are homographs and one is explicitly declared and the other is implicitly declared, then the implicit declaration is not made directly visible.
c) Potentially visible declarations that have the same designator and that are not covered by case b) are not made directly visible unless each of them is either an enumeration literal specification or the declaration of a subprogram.
Noting you have two potentially visible declarations, e.g.:
The errors are :** Error: C:/altera/16.0/multiplexer2.vhd(17): (vcom-1078) Identifier "unsigned" is not directly visible.
Potentially visible declarations are: ieee.NUMERIC_STD.UNSIGNED (subtype declaration) ieee.NUMERIC_BIT.UNSIGNED (type declaration)
unsigned, a type declaration is not visible under rule c) above.
As Jim notes you don't use type unsigned based on type bit_vector, all object declarations present are based on std_logic and not bit.
Further, 16.8.5.1 General paras 1
Four VHDL packages for arithmetic using bit and standard logic values are defined by this standard. The NUMERIC_BIT and NUMERIC_BIT_UNSIGNED packages are based on the VHDL type BIT, while the NUMERIC_STD and NUMERIC_STD_UNSIGNED packages are based on the type STD_ULOGIC.
and para 6 (in part):
The four packages are mutually incompatible, and only one shall be used in any given design unit.
You've demonstrated that incompatibility, attempting to use a declaration that is neither an enumeration literal nor subprogram (not subject to overload resolution).
If you're tool had been -2008 aware it should have provided an error (shall is mandatory, see 1.3.1) and use clauses for both made visible in the same declarative region are detectable (although not a convenient error to detect).
In general you should use the minimum number of use clauses necessary, providing resources needed for a design description to avoid these sorts of issues.
Commenting out the use clause referencing numeric_bit is not sufficient. The base type of CI is std_ulogic (it's type is std_logic). You can convert a std_logic to an unsigned excepted by expressing CI as a an array type:
library ieee;
use ieee.std_logic_1164.ALL;
-- use ieee.numeric_bit.ALL;
use ieee.numeric_std.ALL;
entity multiplexer is
port (
A,B: in std_logic_vector (7 downto 0);
CI: in std_logic;
CO: out std_logic;
ANS: out std_logic_vector (7 downto 0);
OP: in std_logic_vector(1 downto 0);
EN: in std_logic);
end multiplexer;
architecture archi of multiplexer is
signal tmp: std_logic_vector (8 downto 0);
begin
tmp <= std_logic_vector(unsigned(A)+unsigned(B)+unsigned'(""& CI)) when EN =
'1' and OP = "00" else
std_logic_vector(unsigned(A)-unsigned(B)+unsigned'(""& CI)) when EN = '0' and
OP = "01" else
(others => '0');
-- tmp <= std_logic_vector(unsigned(A)+unsigned(B)+unsigned(CI)) when EN =
-- '1' and OP = "00" else
-- std_logic_vector(unsigned(A)-unsigned(B)+unsigned(CI)) when EN = '0' and
-- OP = "01" else
-- (others => '0');
ANS<= tmp(7 downto 0);
CO <= tmp(8);
end archi;
unsigned'(""& CI) qualifies the expression "" & CI (a null array concatenated with CI as type unsigned.
See 9.3.5 Qualified expressions, para 1:
A qualified expression is a basic operation (see 5.1) that is used to explicitly state the type, and possibly the subtype, of an operand that is an expression or an aggregate.
For the array type unsigned concatenation operators are predefined for concatenation between a value of a single dimensional array type and it's element type. See 9.2.5 Adding operators. The string literal "" has a length of zero (15.7 String literals, 5.3.2.2 Index constraints and discrete ranges, para 4), and it's type is context defined by the qualified expression (See 9.3.2 Literals para 5).
Making the above changes and your multiplexer analyzes. It's functionality is not tested lacking a Minimal, Complete, and Verifiable example.

Answer 2

1. to_integer
Look for documentation for numeric_std package. You can't put std_logic_vector to to_integer function. You have to first cast it to unsigned:
signal a: std_logic_vector(8 downto 0);
signal b: std_logic_vector(8 downto 0);
signal res: integer;
res <= to_integer(unsigned(a) + unsigned(b));
But actually, in your case you don't have to do it at all. Just cast std_logic_vector to unsigned (or signed), and then you can safely add it:
tmp <= std_logic_vector(unsigned(A)+unsigned(B)+unsigned(CI));
2. UUU thing
First - as I already told you - you must have all inputs in sensitivity list, if you want to do it without clock. But this will not help, because you are using signals. Remember, that when you assign something to signal, it is not done immediately, but it is only sceduled, to be done after the process. So after line:
tmp <= std_logic_vector((TO_INTEGER(A)+TO_INTEGER(B)+TO_INTEGER(CI)),9);
tmp does not yet contain result, but still has UUU. Then in lines:
ANS<= tmp(7 downto 0);
CO <= tmp(8);
you assign U to ANS and CO. What you can do is to use variables in process, or even better - to put lines:
ANS<= tmp(7 downto 0);
CO <= tmp(8);
outside of the process:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity multiplexer is
port (
A,B: in std_logic_vector (7 downto 0);
CI: in std_logic;
CO: out std_logic;
ANS: out std_logic_vector (7 downto 0);
OP: in std_logic_vector(1 downto 0);
EN: in std_logic);
end multiplexer;
architecture archi of multiplexer is
signal tmp: std_logic_vector (8 downto 0);
begin
process (EN) begin
if (EN = '1') Then
case OP is
when "00" =>
tmp <= std_logic_vector(unsigned(A)+unsigned(B)+unsigned(CI));
when "01" =>
tmp <= std_logic_vector(unsigned(A)-unsigned(B)+unsigned(CI));
when others => NULL;
end case;
else
NULL;
end if;
end process;
ANS<= tmp(7 downto 0);
CO <= tmp(8);
end archi;
or even get rid of process at all:
architecture archi of multiplexer is
signal tmp: std_logic_vector (8 downto 0);
begin
tmp <= std_logic_vector(unsigned(A)+unsigned(B)+unsigned(CI)) when EN = '1' and OP = "00" else
std_logic_vector(unsigned(A)-unsigned(B)+unsigned(CI)) when EN = '1' and OP = "01" else
(others => '0');
ANS<= tmp(7 downto 0);
CO <= tmp(8);
end archi;