I am trying to create an architecture that has the following behaviour:
entity component1 is
generic (
debounce_ticks : natural range 0 to natural'high
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
sclk : in STD_LOGIC;
[...]
);
end component1;
architecture Behavioral of component1 is
signal sclk_debounced : STD_LOGIC;
[...]
begin
debouncer:
if debounce_ticks > 0 generate
sclk_debouncer : entity work.static_debouncer
generic map (
debounce_ticks => debounce_ticks
)
port map (
clk => clk,
pulse_in => sclk,
pulse_out => sclk_debounced
);
else --Or something
sclk_debounced <= sclk
end generate debouncer;
[..]
end Behavioral;
So, I have this signal, which I want to either just connect to an input or loop trough a component, based on a generic.
How can I achieve this?
The if generate statement does not support an else clause, so you need to invert the check to simulate an else. Also you need a second label for the other if generate.
begin
debouncer:
if debounce_ticks > 0 generate
sclk_debouncer : entity work.static_debouncer
generic map (
debounce_ticks => debounce_ticks
)
port map (
clk => clk,
pulse_in => sclk,
pulse_out => sclk_debounced
);
end generate debouncer;
no_debouncer:
if debounce_ticks <= 0 generate
sclk_debounced <= sclk
end generate no_debouncer;
[...]
You need two changes:
component is a reserved word and can't be used as an identifier.
the reserved word generate is missing after else
Renamed entity:
entity component1 is
generic (
debounce_ticks : natural range 0 to natural'high
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
sclk : in STD_LOGIC;
-- [...]
);
end entity component1;
Fixed generate statement:
architecture Behavioral of component1 is
signal sclk_debounced : STD_LOGIC;
-- [...]
begin
debouncer: if debounce_ticks > 0 generate
sclk_debouncer : entity work.static_debouncer
generic map (
debounce_ticks => debounce_ticks
)
port map (
clk => clk,
pulse_in => sclk,
pulse_out => sclk_debounced
);
else generate --Or something
sclk_debounced <= sclk
end generate debouncer;
-- [..]
end architecture Behavioral;
Related
this is my code for dff and multiplexer and shift register, which should rich the output in 4 clocks but it does it in one clock and I could not fix it myself.
this is my dff code:
use IEEE.STD_LOGIC_1164.ALL;
entity DFLipFlop is
Port ( d : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC);
end DFLipFlop;
architecture Behavioral of DFLipFlop is
begin
process(clock,reset)
begin
if(reset ='1')then
q <= '0';
elsif(CLOCK='1' and CLOCK'EVENT)then
q <= d;
end if;
end process;
end Behavioral;
this is my multiplexer code:
-- Company:
-- Engineer:
--
-- Create Date: 08:37:48 04/27/2022
-- Design Name:
-- Module Name: multiplexer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplexer is
Port ( DataIn : in STD_LOGIC;
P_in : in STD_LOGIC;
Selector : in STD_LOGIC;
Output : out STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process(Selector)
begin
if Selector = '0' then
Output <= DataIn ;
else
OutPut <= P_in ;
end if;
end process;
end Behavioral;
this is my shift register code:
-- Company:
-- Engineer:
--
-- Create Date: 08:35:05 04/27/2022
-- Design Name:
-- Module Name: shiftRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shiftRegister is
Port ( DataIn : in STD_LOGIC;
Selector : in STD_LOGIC;
P_in : in STD_LOGIC_VECTOR (3 downto 0);
Clk : in STD_LOGIC;
OutPut : out STD_LOGIC);
end shiftRegister;
architecture structural of shiftRegister is
component DFLipFlop is
Port ( d : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC);
end component DFLipFlop;
component multiplexer is
Port ( DataIn : in STD_LOGIC;
P_in : in STD_LOGIC;
Selector : in STD_LOGIC;
Output : out STD_LOGIC);
end component multiplexer;
signal DFFOutput : STD_LOGIC_VECTOR(3 downto 0);
signal MuxOutput : STD_LOGIC_VECTOR(3 downto 0);
begin
multiplexer0 : multiplexer Port map( DataIn => DataIn , P_in => P_in(3) , Selector => Selector , Output => MuxOutput(0) );
dff_interface0 : DFLipFlop port map( d => MuxOutput(0) , clock => Clk , reset => '0' , q => DFFOutput(0));
multiplexer1 : multiplexer Port map( DataIn => DFFOutput(0) , P_in => P_in(2) , Selector => Selector , Output => MuxOutput(1) );
dff_interface1 : DFLipFlop port map( d => MuxOutput(1) , clock => Clk , reset => '0' , q => DFFOutput(1));
multiplexer2 : multiplexer Port map( DataIn => DFFOutput(1) , P_in => P_in(1) , Selector => Selector , Output => MuxOutput(2) );
dff_interface2 : DFLipFlop port map( d => MuxOutput(2) , clock => Clk , reset => '0' , q => DFFOutput(2));
multiplexer3 : multiplexer Port map( DataIn => DFFOutput(2) , P_in => P_in(0) , Selector => Selector , Output => MuxOutput(3) );
dff_interface3 : DFLipFlop port map( d => MuxOutput(3) , clock => Clk , reset => '0' , q => Output);
end structural;
and this is my test bench:
-- Company:
-- Engineer:
--
-- Create Date: 09:12:38 04/27/2022
-- Design Name:
-- Module Name: C:/Users/ABTIN/Documents/amirkabir un/term 4/Computer Architecture/Lab/HW8/HW8/TestBench.vhd
-- Project Name: HW8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: shiftRegister
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestBench IS
END TestBench;
ARCHITECTURE behavior OF TestBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shiftRegister
PORT(
DataIn : IN std_logic;
Selector : IN std_logic;
P_in : IN std_logic_vector(3 downto 0);
Clk : IN std_logic;
OutPut : OUT std_logic
);
END COMPONENT;
--Inputs
signal DataIn : std_logic := '0';
signal Selector : std_logic := '0';
signal P_in : std_logic_vector(3 downto 0) := "1011";
signal Clk : std_logic := '0';
--Outputs
signal OutPut : std_logic;
-- Clock period definitions
constant Clk_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shiftRegister PORT MAP (
DataIn => DataIn,
Selector => Selector,
P_in => P_in,
Clk => Clk,
OutPut => OutPut
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for Clk_period*10;
DataIn <= '0' ; P_in <= "1011" ; Selector <= '1' ;wait for Clk_period*1;
DataIn <= '1' ; P_in <= "1001" ;wait for Clk_period*2;
-- insert stimulus here
wait;
end process;
END;
I can not figure out what the problem is.
please help.
Your data input signal is not propagated across the shift register in a single clock.
When looking at this simulation, you can see it is the upper bit of your preload data that gets loaded at the clock edge where the cursor is placed. The behavior is consistent with the code.
The detailled explanation is:
at the cursor, Selector is 1, which means the multiplexer will select the P_in value
because the DFF gets the P_in value, it loads it at the cursor and the bit 4 of P_in is 1 so DFFOutput becomes 1 too
If you wanted to propagate a 1 across the shift-register, you should first reset it (to set it to zero) and then give it a 1 on the input.
You should use a proper reset at the begin of the testbench. This way your design gets into a known state.
In your testbench, you assign initial values to the signals but use them in sensitivity lists (the main culprit is selector). Because of this, the output of the multiplexers are undefined as the process was not triggered by a change on the signal.
You should change the testbench to look like this:
-- hold reset state for 100 ns.
wait for Clk_period * 10;
selector <= '0'; -- this assignment triggers the multiplexer processes
p_in <= "1011";
I would also strongly suggest simulating your entire design and exploring the signals inside (I see you use Vivado, it has an integrated simulator; otherwise Intel provides a free Modelsim license if you need it).
If you want to use the Vivado simulator, have a look at UG937.
To get examples of how to implement a particular component in Vivado, you can also look at the Synthesis Guide (UG901). There is an example of the implementation to use for shift registers to make optimal use of the FPGA's resources (other FPGA manufacturers have similar guides, look for synthesis guide in your favorite search engine).
For Vivado, there are also integrated code examples under Tools > Language templates.
Consider this code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_definitions.all;
entity Blink_Entity is
generic (BITWIDTH : integer;
count_to : integer
);
port (
start_button_i : in std_ulogic;
reset_i : in std_ulogic;
clk_i : in std_ulogic;
led_o : in std_ulogic
);
end Blink_Entity;
architecture bhv of Blink_Entity is
signal counter_restart_strobe : std_ulogic := '0';
signal counter_value : std_ulogic_vector(BITWIDTH-1 downto 0);
begin
Counter : entity work.Counter_Entity
generic map (
BITWIDTH => BITWIDTH
)
port map (
clk_i => clk_i,
reset_i => reset_i,
counter_restart_strobe_i => counter_restart_strobe,
counter_value_o => counter_value
);
FSM : entity work.FSM_Entity
generic map (
BITWIDTH => BITWIDTH,
count_to => count_to
)
port map (
start_button_i => start_button_i,
clock_i => clock_i,
reset_i => reset_i,
counter_value_i => counter_value,
counter_restart_strobe_o => counter_restart_strobe,
led_o => led_o
);
end architecture;
And these two entities;
library ieee;
use ieee.std_logic_1164.all;
entity counter is
generic (BITWIDTH : integer);
port( clk_i : in std_ulogic;
reset_i : in std_ulogic;
counter_restart_strobe_i : in std_ulogic;
counter_value_o : out std_ulogic_vector(BITWIDTH downto 0)
);
end counter;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FSM is
generic( BITWIDTH : integer;
count_to : integer
);
port( start_button_i: in std_ulogic;
clock_i: in std_ulogic;
reset_i: in std_ulogic;
counter_value_i: in std_ulogic_vector(BITWIDTH-1 downto 0);
restart_counter_strobe_o : out std_ulogic;
led_o : out std_ulogic
);
end entity;
Now I've setup the compile order that the last one to compile is the Blinking entity,after counter and FSM.This is the error I get;
** Error: (vcom-11) Could not find work.counter_entity.
** Error (suppressible): C:\Users\Hp\Desktop\UE_2\Blinking_Entity.vhd(28): (vcom-1195) Cannot find expanded name "work.Counter_Entity".
** Error: C:\Users\Hp\Desktop\UE_2\Blinking_Entity.vhd(28): Unknown expanded name.
** Error: (vcom-11) Could not find work.fsm_entity.
** Error (suppressible): C:\Users\Hp\Desktop\UE_2\Blinking_Entity.vhd(41): (vcom-1195) Cannot find expanded name "work.FSM_Entity".
** Error: C:\Users\Hp\Desktop\UE_2\Blinking_Entity.vhd(41): Unknown expanded name.
** Note: C:\Users\Hp\Desktop\UE_2\Blinking_Entity.vhd(58): VHDL Compiler exiting
I am not seeing the reason this is occurring. Any thoughts?
Okay so I found the error, a silly one at that.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_definitions.all;
entity Blink_Entity is
generic (BITWIDTH : integer;
count_to : integer
);
port (
start_button_i : in std_ulogic;
reset_i : in std_ulogic;
clk_i : in std_ulogic;
led_o : in std_ulogic
);
end Blink_Entity;
architecture bhv of Blink_Entity is
signal counter_restart_strobe : std_ulogic := '0';
signal counter_value : std_ulogic_vector(BITWIDTH-1 downto 0);
begin
Counter : entity work.counter
generic map (
BITWIDTH => BITWIDTH
)
port map (
clk_i => clk_i,
reset_i => reset_i,
counter_restart_strobe_i => counter_restart_strobe,
counter_value_o => counter_value
);
FSM : entity work.FSM
generic map (
BITWIDTH => BITWIDTH,
count_to => count_to
)
port map (
start_button_i => start_button_i,
clock_i => clock_i,
reset_i => reset_i,
counter_value_i => counter_value,
counter_restart_strobe_o => counter_restart_strobe,
led_o => led_o
);
end architecture;
I used the file names, and not the names of the entities (counter and FSM).
I'd like to conditionally instantiate components using generics set on the command line. I'd prefer to have a string as the generic (i.e. fast or slow) rather than a number.
I can't find any examples of this on stackOverflow so I thought I'd ask.
Here is an example of conditionally instantiating architectures of a component using generics. The same code would work for instantiating different components:
LIBRARY ieee;
use ieee.std_logic_1164.all;
entity dut is
generic (
SPEED : string := "fast"
);
port(
clk : in std_logic;
reset: in std_logic;
start: in std_logic;
done: out std_logic);
end entity dut;
architecture dutarch of dut is
component delay is
port (
clk : in std_logic;
reset: in std_logic;
start: in std_logic;
done: out std_logic
);
end component delay;
begin
d1g: if (SPEED = "fast") generate
d1f : entity work.delay(fast)
port map (
clk => clk,
reset => reset,
start => start,
done => done
);
else generate
d1s : entity work.delay(slow)
port map (
clk => clk,
reset => reset,
start => start,
done => done
);
end generate;
end architecture dutarch;
I'm having trouble using the SB_RGBA_DRV primitive provided for the Lattice ICE40UP fpga.
The Technology Library provides a verilog example which I got to work but when i try using it in VHDL the P&R fails, outputting the following message:
Error: Illegal Connection: Pin 'RGB2' of instance 'myrgb' of type 'SB_RGBA_DRV' should be connected to only one top module port. It is connected to the following terminals :
LED2_obuf/DOUT0
This is my .vhdl file:
library ieee;
use ieee.std_logic_1164.all;
entity led is
port (
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end entity led;
architecture rtl of led is
component SB_HFOSC is
port (
CLKHFEN : in std_logic;
CLKHFPU : in std_logic;
CLKHF : out std_logic
);
end component;
component SB_RGBA_DRV is
generic (
RGB0_CURRENT: string:="0b000000";
RGB1_CURRENT: string:="0b000000";
RGB2_CURRENT: string:="0b000000"
);
port (
RGBPU : in std_logic;
RGBLEDEN : in std_logic;
RGB0PWM : in std_logic;
RGB1PWM : in std_logic;
RGB2PWM : in std_logic;
RGB0 : out std_logic;
RGB1 : out std_logic;
RGB2 : out std_logic
);
end component;
signal int_osc : std_logic;
begin
myosc : SB_HFOSC
PORT MAP (
CLKHFEN => '1',
CLKHFPU => '1',
CLKHF => int_osc
);
myrgb : SB_RGBA_DRV
GENERIC MAP (
RGB0_CURRENT => "0b111111",
RGB1_CURRENT => "0b111111",
RGB2_CURRENT => "0b111111"
)
PORT MAP (
RGBPU => '1',
RGBLEDEN => '1',
RGB0PWM => '1',
RGB1PWM => '1',
RGB2PWM => '1',
RGB0 => LED0,
RGB1 => LED1,
RGB2 => LED2
);
process
begin
wait until int_osc'event;
end process;
end rtl;
The answer to your question is here:
http://we.easyelectronics.ru/teplofizik/podklyuchenie-vstroennogo-modulya-tokovogo-drayvera-fpga-serii-ice5-ice40-ultra.html
(Scroll down.) Yes, it's in Russian. The key is to add the following declaration at the top of your design file:
library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;
The other things that Teplofizik mentions may be useful to know but aren't entirely necessary.
Your code is almost correct with the above addition. I didn't try to build and run Teplofizik's sample code, but I did modify your code (to actually use the on-chip oscillator) and that code is happily running on an "iCE40UP Breakout" board:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;
entity led is
port (
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end entity led;
architecture rtl of led is
-- not necessary - declared in library
--component SB_HFOSC is
-- port (
-- CLKHFEN : in std_logic;
-- CLKHFPU : in std_logic;
-- CLKHF : out std_logic
-- );
--end component;
--
--component SB_RGBA_DRV is
-- generic (
-- RGB0_CURRENT: string:="0b000000";
-- RGB1_CURRENT: string:="0b000000";
-- RGB2_CURRENT: string:="0b000000"
-- );
-- port (
-- RGBPU : in std_logic;
-- RGBLEDEN : in std_logic;
-- RGB0PWM : in std_logic;
-- RGB1PWM : in std_logic;
-- RGB2PWM : in std_logic;
-- RGB0 : out std_logic;
-- RGB1 : out std_logic;
-- RGB2 : out std_logic
-- );
--end component;
signal int_osc : std_logic;
signal count: unsigned(25 downto 0);
signal led0_en: std_logic;
signal led1_en: std_logic;
signal led2_en: std_logic;
begin
myosc : SB_HFOSC
generic map(
CLKHF_DIV => "0b00" -- 00 = 48 MHz, 01 = 24 MHz, 10 = 12 MHZ, 11 = 6 MHz
)
PORT MAP (
CLKHFEN => '1',
CLKHFPU => '1',
CLKHF => int_osc
);
myrgb : SB_RGBA_DRV
GENERIC MAP (
-- RGB0_CURRENT => "0b111111",
-- RGB1_CURRENT => "0b111111",
-- RGB2_CURRENT => "0b111111"
CURRENT_MODE => "0b0", -- 0 = full current, 1 = halve the current
RGB0_CURRENT => "0b000001", -- 4 mA is more than enough
RGB1_CURRENT => "0b000001",
RGB2_CURRENT => "0b000001"
)
PORT MAP (
-- RGBPU => '1', -- this is an SB_RGB_DRV parameter
CURREN => '1',
RGBLEDEN => '1',
-- RGB0PWM => '1', -- boring
-- RGB1PWM => '1',
-- RGB2PWM => '1',
RGB0PWM => led0_en,
RGB1PWM => led1_en,
RGB2PWM => led2_en,
RGB0 => LED0,
RGB1 => LED1,
RGB2 => LED2
);
-- boring
--process
-- begin
-- wait until int_osc'event;
--end process;
-- cycle through LED's
led0_en <= count(25) and count(24);
led1_en <= count(25) and not count(24);
led2_en <= not count(25) and count(24);
count_proc: process(int_osc)
begin
if rising_edge(int_osc) then
count <= count+1;
end if;
end process;
end rtl;
I am trying to make a VGA controller on a DE0 board and have made the following code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY VGA is
PORT (clk : IN std_logic;
vga_hs, vga_vs : OUT std_logic;
vga_r, vga_g, vga_b : OUT std_logic_vector(3 DOWNTO 0));
END ENTITY VGA;
ARCHITECTURE A1 OF VGA IS
SIGNAL rst, clk25 : std_logic;
BEGIN
SYNC1 : ENTITY work.sync(A1)
PORT MAP (clk25, vga_hs, vga_vs, vga_r, vga_g, vga_b);
CLK_25 : ENTITY work.pll(rtl)
PORT MAP (clk, rst, clk25);
END ARCHITECTURE A1;
When I compile the model I get the following error message:
Error (12006): Node instance "altpll_0" instantiates undefined entity "PLL_altpll_0"
I'm instantiating two components the first SYNC1 is the synchronisation counts for a 640 x 480 display the second (CLK_25) is PLL clock generated by quartus II. With the following model:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PLL is
port (
clk_clk : in std_logic := '0'; -- clk.clk
rst_reset : in std_logic := '0'; -- rst.reset
clk_25_clk : out std_logic -- clk_25.clk
);
end entity PLL;
architecture rtl of PLL is
component PLL_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component PLL_altpll_0;
begin
altpll_0 : component PLL_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_reset, -- inclk_interface_reset.reset
read => open, -- pll_slave.read
write => open, -- .write
address => open, -- .address
readdata => open, -- .readdata
writedata => open, -- .writedata
c0 => clk_25_clk, -- c0.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
end architecture rtl; -- of PLL
How can i directly instantiate pll(rtl) from the working library ?
Generate the PLL with the MegaWizard in Quartus Prime, and then include the generated .qip file in the design. I assume that the MegaWizard is used to generate PLL_altpll_0 in your example.
The generated PLL entity is then compiled into work (or another library which is then shown in the .qip file), and you can then instantiate the PLL with entity instantiation, and thus leave out the redundant component declaration in the architecture that uses the generated PLL. Code like, assuming workPLL_altpll_0 is compiled to work library:
altpll_0 : entity work.PLL_altpll_0
port map (