I have got the number 317 saved in 2 bytes (00000001 00111101) and it should be transfered via SPI (serial) to a slave device.
The device expect the two bytes B11 and B12, but in a certain order:
"The highest bits of the data words are send first and the lowest bits
are send last, that is, byte B11 is the highest byte and byte B12 is
the lowest byte."
My question is, what do they exactly mean? Am I supposed to flip the bytes itselves (10000000 10111100) or to flip bytes AND bits (10111100 10000000)?
Flip the bytes. Or switch , rather:
00000001 00111101
->
00111101 00000001
This is known as endianness (which should help you find related questions)
Related
First I want to apologize because English is not my native language. I'm taking CS50 Introduction to Computer Science course and I've come across the concepts of 'Endianness' and 'Word size' and even though I think I've understood them pretty well, there's still some confusion.
As far as I know, 'Word size' refers to the number of bytes a processor can read or write from memory in one cycle, the instruction bytes it can send at a time, and the max size of memory addresses also; being them 4 bytes in 32-bits architectures and 8 bytes in 64-bits architectures. Correct me if I'm wrong with this.
Now, 'Endianness' refers to the ordering of bytes of a multi-byte data type (like an int or float, not a char) when the processor handles them, to either storage or transmit them. According to some definitions I've read, this concept is linked to a word size. For example, in Wikipedia, it says: "endianness is the ordering or sequencing of bytes of a word of digital data". Big-endian means when the most significant byte is placed in the smallest memory address and low-endian when the least significant byte is placed in the smallest memory address instead.
I've seen many examples and diagrams like this one:
Little-endian / Big-endian explanation diagram
I understand big-endian very well and little-endian when the data type being processed has a size equal or smaller than the word size is also clear. But what happens when it's bigger than the word size? Imagine an 8-byte data type in a 32-bit little-endian architecture (4-byte words), how are the bytes actually stored:
Ordering #1:
----------------->
lower address to higher address
b7 b6 b5 b4 |b3 b2 b1 b0
word 0 |word 1
Ordering #2:
----------------->
lower address to higher address
b3 b2 b1 b0 | b7 b6 b5 b4
word 0 | word 1
I've found mixed answers to this question, and I wanted to have this concept clear to continue. Thank you in advance!
I want to know if I have solved this problem about direct mapped cache correctly. I need to calculate the position of the block in cache and find its tag.
Given that the CACHE has 1024 BLOCK's and there are 64 bytes per BLOCK, in which position of the CACHE will the address 5C892D0(hex) be stored?
The address 5C892D0 in binary code is:
101 1100 1000 1001 0010 1101 0000.
As there are 512 bits in every block I know that the rightmost 9 bits (2^9 = 512) is the position in the MAIN MEMORY and the previous 10 bits (2^10=1024) is the position in the CACHE. The remaining bits form the TAG.
So the block position in the CACHE of this address is 0001001001 or the 73rd BLOCK in CACHE, and the TAG is 10111001.
There is a small mistake in your computation
Because there is 512 bits in every block i know that the rightest 9 bits
(2^9 = 512)
Blocks are 64 bytes. The lowest bits are for the offset that indicates the byte position within the block and only 6 bits are required. You considered the number of bits (512=64x8), but addresses are byte addresses and it is incorrect.
You are right the 10 next bits are the index that selects a block among 1024 in a direct map cache.
And the tag is formed by the remaining bits
Hence offset= 01 0000
index=1001001011=587
Tag=0101 1100 1000
In the documentation to MMIX machine mmix-doc page 3 paragraph 4:
We use the notation to stand for a number consisting of
consecutive bytes starting at location . (The notation
means that the least significant t bits of k are set to
0, and only the least 64 bits of the resulting address are retained.
...
The notation M2t[k] is just a formal symbolism to express an address divisible by 2t.
This is confirmed just after the definition
All accesses to 2t-byte quantities by MMIX are aligned, in the
sense that the first byte is a multiple of 2t.
Most architectures, specially RISC ones, require a memory access to be aligned, this means that the address must be a multiple of the size accessed.
So, for example, reading a 64 bits word (an octa in MMIX notation) from memory require the address to be divisible by 8 because MMIX memory is byte addressable(1) and there are 8 bytes in an octa.
If all the possible data sizes are power of two we see a pattern emerge:
Multiples of Multiples of Multiples of
2 4 8
0000 0000 0000
0010 0100 1000
0100 1000
0110 1100
1000
1010
1100
1110
Multiples of 2 = 21 have the least bit always set to zero(2), multiples of 4 = 22 have the the two least bits set to zero, multiples of 8 = 23 have the three least bits set to zero and so on.
In general multiples of 2t have the least t bits set to zero.
You can formally prove this by induction over t.
A way to align a 64 bit number (the size of the MMIX address space) is to clear its lower t bits, this can be done by performing an AND operation with a mask of the form
11111...1000...0
\ / \ /
64 - t t
Such mask can be expressed as 264 - 2t.
264 is a big number for an example, lets pretend the address space is only 25.
Lets say we have the address 17h or 10111b in binary and lets say we want to align it to octas.
Octas are 8 bytes, 23 so we need to clear the lower 3 bits and preserve the other 2 bits.
The mask to use is 11000b or 18h in hexadecimal. This number is 25-23 = 32 - 8 = 24 = 18h.
If we perform the boolean AND between 17h and 18h we get 10h which is the aligned address.
This explains the notation k ∧ (264 − 2t) used short after, the "wedge" symbol ∧ is a logic AND.
So this notation just "pictures" the steps necessary to align the address k.
Note that the notation k ∨ (2t − 1) is also introduced, this is the complementary, ∨ is the OR and the whole effect is to have the lower t bits set to 1.
This is the greatest address occupied by an aligned access of size 2t.
The notation itself is used to explain the endianess.
If you wonder why aligned access are important, it has to do with hardware implementation.
Long story short the CPU interface to the memory has a predefined size despite the memory being byte addressable, say 64 bits.
So the CPU access the memory in blocks of 64 bits each one starting at an address multiple of 64 bits (i.e. aligned on 8 bytes).
Accessing an unaligned location may require the CPU to perform two access:
CPU reading an octa at address 2, we need bytes at 2, 3, 4 and 5.
Address 0 1 2 3 4 5 6 7 8 9 A B ...
\ / \ /
A B
CPU read octa at 0 (access A) and octa at 4 (access B), then combines the two reads.
RISC machine tends to avoid this complexity and entirely forbid unaligned access.
(1) Quoting: "If k is any unsigned octabyte, M[k] is a 1-byte
quantity".
(2) 20 = 1 is the only odd power of two, so you can guess that by removing it we only get even numbers.
If we have to receive a data from sender as a chunk of bits (say 8 bits).
But, the transferring is unreliable which result in bit-lost. (Not bit-flip)
That mean, any bit in the chunk can be absent and receiver would receive only 7 bits.
I studied some error-correction coding, such as 'Hamming code'. But, the code is designed to recover fliped-bit not lost-bit in this situation.
If you are happy with a low entropy code and you can detect an end-of-message, you can simply send each bit twice.
This code can recover from any number of deletions that happen in different runs:
On receiving, find all odd-sized runs and extend them by one bit. If you end up with less than the expected count of bits, you are unable to recover from multiple deletion.
If you want to ensure a fixed error rate that can be recovered, use bit-stuffing.
Example:
0110
encoded as:
00 11 11 00
a double error occurs:
0x 11 x1 00
received:
011100
'0' and '111' are odd-sized runs. Fix:
00111100
we have 8 bits, and have recovered from a double error.
decode:
0110
Example 2:
0101
encoded as
00110011
transmitted as
0xxx0011
received as
00011
corrected as
000011
decoded as
001
which is shorter than expected. A transmission error has occured.
Example 3 (bit stuffing after a run of 3 bits):
0000 1111
stuffed as
00010 11101
sent as
0000001100 1111110011
I'm taking a programming fundamentals course and currently I'm on the chapter where it talks about computer organization and operations on bits - how the CPU (ALU, CU, registers, etc.) works.
I have a fairly good understanding of the binary language. I understand sign/magnitude format/ 1's complement, 2's complement, etc.
In the book I've learned that a nibble = 4 bits, 8 bits = 1 byte next is a word - which is usually in groups: 8 bits, 16 bits, 32 bits or 64 bits (so on), and all this makes perfect sense to me. Here's my homework question which is kind of confusing to me:
"A computer has 64 MB of memory, Each word is 4 bytes. How many bits are needed to address each single word in memory?"
Well, I'm confused now. The book just told me that a word is typically in multiples of 8.
However I know that 1 byte = 8 bits, so since there are 4 bytes and 1 byte = 8 bytes, would it be correct to think that 4 bytes x 8 bits = 32 bits? Is this the answer?
A 1-bit address can address two words (0, 1).
A 2-bit address can address four words (00, 01, 10, 11).
A 3-bit address can address eight words (000, 001, 010, 011, 100, 101, 110, 111).
So first answer: How many words do you have? Then answer: How many bits does your address need in order to address them?
64MB = 67108864 Bytes/4 Bytes = 16777216 words in memory, and each single word can thus be addressed in 24 bits (first word has address 000000000000000000000000 and last has address 111111111111111111111111). Also 2 raised to 24 = 16777216, so 24 bits are needed to address each word in memory.
The requirement is to represent each memory word with an address, which is in bits, in such a way that each and every word can be represented.
For example, to represent 4 words, you need 4 addresses, 2 raised to 2 is 4, so you need two bits. 00 is the address of the first word, 01 is the address of the second word, 10 is the address of the third word, and 11 is the address of the 4th word.
For 8 words, you need 8 addresses, and 2 raised to 3 is 8, so 3 bits are needed. 000, 001, 010, 011, 100, 101, 110, 111 are the 8 addresses.
1 byte = 8 bits, so since there are 4 bytes and 1 byte = 8 bites Would it be correct to think 4bytes x 8 bites = 32 bits?? being the answer???
No, that's not the answer. If your computer has 64 MB of memory and each word is 4 bytes, how many words are there in your memory? How much bits would you need to address each word (bits needed to represent a number from 0 to number of words - 1).
The formula being:
log (Memory Size/Addressable Unit Size) / log 2
Example1:
How many address bits are required to address 16GBytes of memory, where each addressable unit is 1 byte wide?
Ans: log(16*1024*1024*1024/1)/log2 = 34 bits
Example2:
How many address bits are required to address 16GBytes of memory, where each addressable unit is 2 bytes wide?
Ans: log(16*1024*1024*1024/2)/log2 = 33 bits
Example3:
How many address bits are required to address 64MBytes of memory, where each addressable unit is 4 bytes wide?
Ans: log(64*1024*1024/4)/log2 = 24 bits
Example3:
How many address bits are required to address 16MBytes of memory, where each addressable unit is 1 byte wide?
Ans: log(16*1024*1024/1)/log2 = 24 bits