I'm trying to extract filenames from rar packages in a directory. I'm using 7z which returns a multi-line string, and would like to search the output for "mkv", "avi", or "srt" files.
Here's my code:
ROOT_DIR = "/users/ken/extract"
# Check each directory for Rar packages
# Returns an arary of directories with filenames from the rar's
def checkdirs()
pkgdirs = {}
Dir.foreach(ROOT_DIR) do |d|
if !Dir.glob("#{ROOT_DIR}/#{d}/*.rar").empty?
rarlist = `7z l #{ROOT_DIR}/#{d}/*.rar`
puts rarlist # Returns multilinen output from 7z l
puts rarlist.scan('*.mkv').first
pkgdirs[d] = 'filename'
end
end
pkgdirs
end
I can get the 7z output but I can't figure out how to search the output for my strings. How can I search the output and return the matching lines?
This is an example of the 7z output:
7-Zip [64] 16.02 : Copyright (c) 1999-2016 Igor Pavlov : 2016-05-21
p7zip Version 16.02 (locale=utf8,Utf16=on,HugeFiles=on,64 bits,8 CPUs x64)
Scanning the drive for archives:
1 file, 15000000 bytes (15 MiB)
Listing archive: Gotham.S03E19.HDTV.x264-KILLERS/gotham.s03e19.hdtv.x264-killers.rar
--
Path = Gotham.S03E19.HDTV.x264-KILLERS/gotham.s03e19.hdtv.x264-killers.rar
Type = Rar
Physical Size = 15000000
Total Physical Size = 285988640
Characteristics = Volume FirstVolume VolCRC
Solid = -
Blocks = 1
Multivolume = +
Volume Index = 0
Volumes = 20
Date Time Attr Size Compressed Name
------------------- ----- ------------ ------------ ------------------------
2017-05-23 02:30:52 ..... 285986500 285986500 Gotham.S03E19.HDTV.x264-KILLERS.mkv
------------------- ----- ------------ ------------ ------------------------
2017-05-23 02:30:52 285986500 285986500 1 files
------------------- ----- ------------ ------------ ------------------------
2017-05-23 02:30:52 285986500 285986500 1 files
Archives: 1
Volumes: 20
Total archives size: 285988640
I expect this output:
2017-05-23 02:30:52 ..... 285986500 285986500 Gotham.S03E19.HDTV.x264-KILLERS.mkv
You can use this:
puts rarlist.scan(/^.*\.mkv/)
The regex will match from the beginning of lines.
To match .mkv, .avi, or .srt, you can use:
rarlist.scan(/(^.*\.(mkv|avi|srt))/) {|a,_| puts a}
The solution is much simpler than what you're making it.
Starting with:
TARGET_EXTENSIONS = %w[mkv avi srt]
TARGET_EXTENSION_RE = /\.(?:#{ Regexp.union(TARGET_EXTENSIONS).source})/
# => /\.(?:mkv|avi|srt)/
output = <<EOT
7-Zip [64] 16.02 : Copyright (c) 1999-2016 Igor Pavlov : 2016-05-21
p7zip Version 16.02 (locale=utf8,Utf16=on,HugeFiles=on,64 bits,8 CPUs x64)
Scanning the drive for archives:
1 file, 15000000 bytes (15 MiB)
Listing archive: Gotham.S03E19.HDTV.x264-KILLERS/gotham.s03e19.hdtv.x264-killers.rar
--
Path = Gotham.S03E19.HDTV.x264-KILLERS/gotham.s03e19.hdtv.x264-killers.rar
Type = Rar
Physical Size = 15000000
Total Physical Size = 285988640
Characteristics = Volume FirstVolume VolCRC
Solid = -
Blocks = 1
Multivolume = +
Volume Index = 0
Volumes = 20
Date Time Attr Size Compressed Name
------------------- ----- ------------ ------------ ------------------------
2017-05-23 02:30:52 ..... 285986500 285986500 Gotham.S03E19.HDTV.x264-KILLERS.mkv
------------------- ----- ------------ ------------ ------------------------
2017-05-23 02:30:52 285986500 285986500 1 files
------------------- ----- ------------ ------------ ------------------------
2017-05-23 02:30:52 285986500 285986500 1 files
Archives: 1
Volumes: 20
Total archives size: 285988640
EOT
All it takes is to iterate over the lines in the output and puts the matches:
puts output.lines.grep(TARGET_EXTENSION_RE)
Which would output:
2017-05-23 02:30:52 ..... 285986500 285986500 Gotham.S03E19.HDTV.x264-KILLERS.mkv
The above is a basic solution, but there are things that could be done to speed up the code, depending on the output being received:
TARGET_EXTENSIONS = %w[mkv avi srt].map { |e| '.' << e } # => [".mkv", ".avi", ".srt"]
puts output.split(/\r?\n/).select { |l| l.end_with?(*TARGET_EXTENSIONS) }
I'd have to run benchmarks, but that should be faster, since regular expressions can drastically slow code if not written correctly.
You could try:
TARGET_EXTENSION_RE = /\.(?:#{ Regexp.union(TARGET_EXTENSIONS).source})$/
# => /\.(?:mkv|avi|srt)$/
puts output.split(/\r?\n/).grep(TARGET_EXTENSION_RE)
as anchored patterns are much faster than unanchored.
If the 7z archives will generate huge listings (in the MB range) it'd be better to iterate over the input to avoid scalability issues. In the above example output.lines would be akin to slurping the output. See "Why is "slurping" a file not a good practice?" for more information.
Related
so I have a .vmdk archive that is created by Memu (android emulator) , and I need to extract one file from it using command line.
I am able to do it using 7zip GUI drag and drop, but from the command line it does not work. Open for any other options besides 7zip!
Thank you!
Below is the output using the command-
7z.exe l D:\vms\MEmu\MEmu96-2022102700023FFF-disk2.vmdk
C:\Program Files\7-Zip>7z.exe l
D:\vms\MEmu\MEmu96-2022102700023FFF-disk2.vmdk
7-Zip 19.00 (x64) : Copyright (c) 1999-2018 Igor Pavlov : 2019-02-21
Scanning the drive for archives: 1 file, 3719291904 bytes (3547 MiB)
Listing archive: D:\vms\MEmu\MEmu96-2022102700023FFF-disk2.vmdk
-- Path = D:\vms\MEmu\MEmu96-2022102700023FFF-disk2.vmdk Open WARNING: Can not open the file as [VMDK] archive Type = VHD Physical Size =
3719291904 Offset = 0 Created = 2022-05-28 03:49:29 Cluster Size =
2097152 Method = Dynamic Total Physical Size = 3719291904 Creator
Application = vbox 6.1 Host OS = Windows Saved State = - ID =
19112220CCCCCCCCCCCC000000000000
---- Size = 68826850816 Packed Size = 3718250496 Created = 2022-05-28 03:49:29
-- Path = MEmu96-2022102700023FFF-disk2.mbr Type = MBR Physical Size = 68826850816
Date Time Attr Size Compressed Name
..... 1048576 1048576 0.img
..... 1048576 1048576 1.img
..... 68823705088 68823705088 2.img
68825802240 68825802240 3 files
Warnings: 1
Given a network (take OpenPCDet as example), which runs on distributed GPUs.
How could I know which module costs the most of time during training?
I don't want to manually test each module by
torch.cuda.synchronize()
start = time.time()
result = model(input)
torch.cuda.synchronize()
end = time.time()
And with torch.autograd.profiler.profile(enabled=True) as prof: only shows me the CPU time:
(which doesn't seem right either, I am not sure I used it properly)
----------------------------- ------------ ------------ ------------ ------------ ------------ ------------
Name Self CPU % Self CPU CPU total % CPU total CPU time avg # of Calls
----------------------------- ------------ ------------ ------------ ------------ ------------ ------------
aten::randperm 28.77% 77.040us 61.28% 164.094us 82.047us 2
aten::random_ 22.25% 59.584us 22.25% 59.584us 29.792us 2
aten::empty 21.79% 58.333us 21.79% 58.333us 19.444us 3
aten::item 10.91% 29.225us 21.22% 56.807us 28.403us 2
aten::_local_scalar_dense 10.30% 27.582us 10.30% 27.582us 13.791us 2
aten::scalar_tensor 4.19% 11.222us 4.19% 11.222us 11.222us 1
aten::resize_ 0.94% 2.507us 0.94% 2.507us 1.253us 2
aten::is_floating_point 0.85% 2.268us 0.85% 2.268us 1.134us 2
----------------------------- ------------ ------------ ------------ ------------ ------------ ------------
Self CPU time total: 267.761us
Answers that only work on a single GPU are also welcomed.
In that case, you'd have to enable cuda on your model, input (.cuda() or .to(device)) and on the profiler
with profile(activities=[ProfilerActivity.CPU, profilerActivity.CUDA]) as prof: as described in the docu
If you want to profile the training performance, it's also important to call loss.backward() inside the profiler context/with block, as the backward pass performance might differ from the forward pass by quite a bit.
Ps.: I also find a bit easier to read the profiler output as a Pandas DataFrame:
df = pd.DataFrame({e.key:e.__dict__ for e in prof.key_averages()}).T
df[['count', 'cpu_time_total', 'cuda_time_total']].sort_values(['cuda_time_total', 'cpu_time_total'], ascending=False)
I have a very long list with hits from a HMMer search in the following form:
Query: Alvin_0001|ID:9263667| [L=454]
Description: chromosomal replication initiator protein DnaA [Allochromatium vinosum DSM 180]
Scores for complete sequence (score includes all domains):
--- full sequence --- --- best 1 domain --- -#dom-
E-value score bias E-value score bias exp N Model Description
------- ------ ----- ------- ------ ----- ---- -- -------- -----------
7.5e-150 497.8 0.2 9e-150 497.5 0.2 1.0 1 COG0593
8e-11 40.6 0.5 1.5e-10 39.7 0.5 1.6 1 COG1484
4.5e-07 28.1 0.2 6e-07 27.7 0.2 1.1 1 COG1373
2.5e-05 22.3 0.1 3.4e-05 21.8 0.1 1.4 1 COG1485
Query: Alvin_0005|ID:9265207| [L=334]
Description: hypothetical protein [Allochromatium vinosum DSM 180]
Scores for complete sequence (score includes all domains):
--- full sequence --- --- best 1 domain --- -#dom-
E-value score bias E-value score bias exp N Model Description
------- ------ ----- ------- ------ ----- ---- -- -------- -----------
------ inclusion threshold ------
0.018 13.4 12.9 0.068 11.5 3.6 2.2 2 COG3247
0.024 13.1 9.0 0.053 12.0 9.0 1.5 1 COG2246
0.046 12.4 7.3 0.049 12.4 5.3 1.8 1 COG2020
Query: Alvin_0004|ID:9265206| [L=154]
Description: hypothetical protein [Allochromatium vinosum DSM 180]
Scores for complete sequence (score includes all domains):
--- full sequence --- --- best 1 domain --- -#dom-
E-value score bias E-value score bias exp N Model Description
------- ------ ----- ------- ------ ----- ---- -- -------- -----------
[No hits detected that satisfy reporting thresholds]
This file contains so much information that I am not interested in, so I need a script that only outputs certain values, that is the line with Query: and the first COG#### in the column Model
So as an expected output (tab delimited file would be the best):
Query: Alvin_0001|ID:9263667| [L=454] COG0593
Query: Alvin_0005|ID:9265207| [L=334] COG3247
Query: Alvin_0004|ID:9265206| [L=154]
note that in the last line, no COG has been found
Now the file structure is a bit too complicated for me to use a simple grep or awk command:
In the first block, the 1st and the 6st line would be the target (awk '/Query: /{nr[NR]; nr[NR+6]}; NR in nr')
In the second block, it is the 1st and the 7th line
and in the third, there is only the line with Query
So what would be now a good approach to parse this file?
Short awk solution:
awk '/^Query:/{ if(q) print q; q=$0 }q && $9~/^COG.{4}$/{ printf("%s\t%s\n",q,$9); q="" }
END{ if(q) print q }' file
The output:
Query: Alvin_0001|ID:9263667| [L=454] COG0593
Query: Alvin_0005|ID:9265207| [L=334] COG3247
Query: Alvin_0004|ID:9265206| [L=154]
Details:
/^Query:/{ q=$0 } - capturing "Query" line
q && $9~/^COG.{4}$/ - capturing the first "Model" field value (ensured by resetting the preceding "Query" line q="")
$ cat tst.awk
BEGIN { OFS="\t" }
/^Query/ { qry=$0 }
$1 ~ /^[0-9]/ { if (qry!="") print qry, $9; qry="" }
/\[No hits/ { print qry }
$ awk -f tst.awk file
Query: Alvin_0001|ID:9263667| [L=454] COG0593
Query: Alvin_0005|ID:9265207| [L=334] COG3247
Query: Alvin_0004|ID:9265206| [L=154]
i am working on AES code and my aim is to create an architecture which will give the fastest performance. hence i need to determine the delay from the time input is given and the final output is obtained. the design is to be implemented on fpga. i need to find the delay via xilinx simulation and design summary. however i fail to understand the various reports.
for model one i am giving the 3 reports from design summary.
synthesis report
place and route report
static timing report
static timing report
--------------------------------------------------------------------------------
Release 9.2i Trace
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
C:\Xilinx92i\bin\nt\trce.exe -ise C:/Xilinx92i/sbox/sbox.ise -intstyle ise -e 3
-s 5 -xml dynamic5stage dynamic5stage.ncd -o dynamic5stage.twr
dynamic5stage.pcf
Design file: dynamic5stage.ncd
Physical constraint file: dynamic5stage.pcf
Device,package,speed: xc3s200,pq208,-5 (PRODUCTION 1.39 2007-04-13)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock SYS_CLK
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
BYTE_IN<0> | 2.659(R)| 0.515(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<1> | 3.216(R)| 0.381(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<2> | 3.373(R)| 0.453(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<3> | 3.155(R)| 0.001(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<4> | 3.419(R)| 0.663(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<5> | 4.055(R)| 0.118(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<6> | 3.389(R)| 0.545(R)|SYS_CLK_BUFGP | 0.000|
BYTE_IN<7> | 3.151(R)| 0.389(R)|SYS_CLK_BUFGP | 0.000|
RST | 2.750(R)| 0.970(R)|SYS_CLK_BUFGP | 0.000|
s | 3.140(R)| 0.344(R)|SYS_CLK_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock SYS_CLK to Pad
---------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
---------------+------------+------------------+--------+
SUB_BYTE_OUT<0>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<1>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<2>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<3>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<4>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<5>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<6>| 6.404(R)|SYS_CLK_BUFGP | 0.000|
SUB_BYTE_OUT<7>| 6.403(R)|SYS_CLK_BUFGP | 0.000|
---------------+------------+------------------+--------+
Clock to Setup on destination clock SYS_CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SYS_CLK | 3.612| | | |
---------------+---------+---------+---------+---------+
Analysis completed Sat Nov 29 11:39:23 2014
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 93 MB
place & route report
Release 9.2i par J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
ACER-PC:: Sat Nov 29 11:38:52 2014
par -w -intstyle ise -ol std -t 1 dynamic5stage_map.ncd dynamic5stage.ncd
dynamic5stage.pcf
Constraints file: dynamic5stage.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx92i.
"dynamic5stage" is an NCD, version 3.1, device xc3s200, package pq208, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.39 2007-04-13".
Device Utilization Summary:
Number of BUFGMUXs 1 out of 8 12%
Number of External IOBs 19 out of 141 13%
Number of LOCed IOBs 0 out of 19 0%
Number of Slices 62 out of 1920 3%
Number of SLICEMs 0 out of 960 0%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
REAL time consumed by placer: 16 secs
CPU time consumed by placer: 10 secs
Writing design to file dynamic5stage.ncd
Total REAL time to Placer completion: 17 secs
Total CPU time to Placer completion: 11 secs
Starting Router
Phase 1: 482 unrouted; REAL time: 18 secs
Phase 2: 436 unrouted; REAL time: 18 secs
Phase 3: 178 unrouted; REAL time: 18 secs
Phase 4: 178 unrouted; (0) REAL time: 18 secs
Phase 5: 180 unrouted; (0) REAL time: 18 secs
Phase 6: 0 unrouted; (87) REAL time: 19 secs
Phase 7: 0 unrouted; (87) REAL time: 19 secs
Updating file: dynamic5stage.ncd with current fully routed design.
Phase 8: 0 unrouted; (0) REAL time: 20 secs
Phase 9: 0 unrouted; (0) REAL time: 20 secs
Total REAL time to Router completion: 20 secs
Total CPU time to Router completion: 13 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| SYS_CLK_BUFGP | BUFGMUX6| No | 45 | 0.036 | 0.916 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 0.832
The MAXIMUM PIN DELAY IS: 2.272
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 1.786
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
337 142 2 0 0 0
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net SYS | SETUP | N/A| 3.612ns| N/A| 0
_CLK_BUFGP | HOLD | 0.702ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 21 secs
Total CPU time to PAR completion: 15 secs
Peak Memory Usage: 136 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file dynamic5stage.ncd
PAR done!
synthesis report
Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 4.04 s | Elapsed : 0.00 / 4.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 4.04 s | Elapsed : 0.00 / 4.00 s
--> Reading design: dynamic5stage.prj
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "dynamic5stage.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "dynamic5stage"
Output Format : NGC
Target Device : xc3s200-5-pq208
---- Source Options
Top Module Name : dynamic5stage
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : dynamic5stage.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx92i/sbox/dynamic5stage.vhd" in Library work.
Entity <dynamic5stage> compiled.
Entity <dynamic5stage> (Architecture <Behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <dynamic5stage> in library <work> (architecture <Behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <dynamic5stage> in library <work> (Architecture <Behavioral>).
INFO:Xst:1561 - "C:/Xilinx92i/sbox/dynamic5stage.vhd" line 278: Mux is complete : default of case is discarded
Entity <dynamic5stage> analyzed. Unit <dynamic5stage> generated.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 1
16x4-bit ROM : 1
# Registers : 13
4-bit register : 12
8-bit register : 1
# Xors : 89
1-bit xor2 : 56
1-bit xor3 : 24
1-bit xor4 : 1
2-bit xor2 : 6
4-bit xor2 : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx92i.
INFO:Xst:2506 - Unit <dynamic5stage> : In order to maximize performance and save block RAM resources, the small ROM <Mrom_GALOIS_MUL_INV> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
INFO:Xst:2261 - The FF/Latch <STAGE2_1_3> in Unit <dynamic5stage> is equivalent to the following FF/Latch, which will be removed : <STAGE2_2_1>
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# ROMs : 1
16x4-bit ROM : 1
# Registers : 55
Flip-Flops : 55
# Xors : 89
1-bit xor2 : 56
1-bit xor3 : 24
1-bit xor4 : 1
2-bit xor2 : 6
4-bit xor2 : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <dynamic5stage> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dynamic5stage, actual ratio is 3.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 55
Flip-Flops : 55
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : dynamic5stage.ngr
Top Level Output File Name : dynamic5stage
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 19
Cell Usage :
# BELS : 114
# LUT2 : 22
# LUT2_D : 4
# LUT2_L : 1
# LUT3 : 14
# LUT3_L : 2
# LUT4 : 49
# LUT4_D : 3
# LUT4_L : 12
# MUXF5 : 7
# FlipFlops/Latches : 55
# FDR : 54
# FDRS : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 18
# IBUF : 10
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200pq208-5
Number of Slices: 61 out of 1920 3%
Number of Slice Flip Flops: 55 out of 3840 1%
Number of 4 input LUTs: 107 out of 3840 2%
Number of IOs: 19
Number of bonded IOBs: 19 out of 141 13%
Number of GCLKs: 1 out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
SYS_CLK | BUFGP | 55 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 4.822ns (Maximum Frequency: 207.394MHz)
Minimum input arrival time before clock: 6.639ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'SYS_CLK'
Clock period: 4.822ns (frequency: 207.394MHz)
Total number of paths / destination ports: 242 / 43
-------------------------------------------------------------------------
Delay: 4.822ns (Levels of Logic = 3)
Source: STAGE3_3_0 (FF)
Destination: STAGE4_2_3 (FF)
Source Clock: SYS_CLK rising
Destination Clock: SYS_CLK rising
Data Path: STAGE3_3_0 to STAGE4_2_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 4 0.626 1.074 STAGE3_3_0 (STAGE3_3_0)
LUT4_D:I0->O 2 0.479 0.768 Mxor_GAL2_MUL_31_xor0000_xo<1>1 (GAL2_MUL_31_xor0000)
LUT4:I3->O 1 0.479 0.740 Mxor_OUTPUT1_xor0000_Result<1>11 (N211)
LUT4:I2->O 1 0.479 0.000 Mxor_OUTPUT1_xor0000_Result<1> (GALOIS_MUL_3<3>)
FDR:D 0.176 STAGE4_2_3
----------------------------------------
Total 4.822ns (2.239ns logic, 2.583ns route)
(46.4% logic, 53.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SYS_CLK'
Total number of paths / destination ports: 168 / 76
-------------------------------------------------------------------------
Offset: 6.639ns (Levels of Logic = 5)
Source: BYTE_IN<4> (PAD)
Destination: STAGE1_2_1 (FF)
Destination Clock: SYS_CLK rising
Data Path: BYTE_IN<4> to STAGE1_2_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 0.715 1.201 BYTE_IN_4_IBUF (BYTE_IN_4_IBUF)
LUT2:I0->O 2 0.479 0.804 GALOIS_ADD_1<0>31 (GALOIS_ADD_1<0>_bdd5)
LUT4:I2->O 1 0.479 0.976 GALOIS_ADD_1<0>11 (GALOIS_ADD_1<0>_bdd0)
LUT3:I0->O 1 0.479 0.851 GALOIS_ADD_1<1>_SW0 (N25)
LUT4:I1->O 1 0.479 0.000 GALOIS_ADD_1<1> (GALOIS_ADD_1<1>)
FDR:D 0.176 STAGE1_2_1
----------------------------------------
Total 6.639ns (2.807ns logic, 3.832ns route)
(42.3% logic, 57.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SYS_CLK'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 6.216ns (Levels of Logic = 1)
Source: OUTPUT_LATCH_7 (FF)
Destination: SUB_BYTE_OUT<7> (PAD)
Source Clock: SYS_CLK rising
Data Path: OUTPUT_LATCH_7 to SUB_BYTE_OUT<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.626 0.681 OUTPUT_LATCH_7 (OUTPUT_LATCH_7)
OBUF:I->O 4.909 SUB_BYTE_OUT_7_OBUF (SUB_BYTE_OUT<7>)
----------------------------------------
Total 6.216ns (5.535ns logic, 0.681ns route)
(89.0% logic, 11.0% route)
=========================================================================
CPU : 29.56 / 34.76 s | Elapsed : 29.00 / 34.00 s
-->
Total memory usage is 205164 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 3 ( 0 filtered)
To measure the performance of your AES block, you can multiply the autotimespec value of 3.612ns from the bottom of the place and route report, with the number of pipeline stages in your system. You write that you have 5 pipeline stages currently, so the total time through the system will be 5*3.612ns = 18.060ns. If you add another pipeline stage in the hope that it will make the system faster, then the clock must be able to run at 18.060ns/6 = 3.010 ns for the added pipeline stage to improve your performance.
The tool has calculated a minimum clock period of 3.612ns = 276 MHz, but if you constrain the sys_clk to be faster than that it might be able to make it faster.
I have few mp3 files as binary strings with same number of channels and same sample rate. I need to concatenate them in memory without using command line tools.
Currently I just do string concatenation, like this:
out = ''
mp3s.each { |mp3| out << mp3 }
Audio players can play the result, but with some warnings, because mp3 headers were not handled correctly as far as I understand.
Is there a way to proceed the concatenation in more correct way?
After reading this article about MP3 in russian I came up with solution.
You must be able to get complete ID3 specification at http://id3.org/ but it seems to be down at the moment.
Usually Mp3 file have the next format:
[ID3 head(10 bytes) | ID3 tags | MP3 frames ]
ID3 is not part of MP3 format, but it's kind of container which is used to put information like artists, albums, etc...
The audio data itself are stored in MP3 frames.Every frame starts with 4 bytes header which provides meta info (codecs, bitrate, etc).
Every frame has fixed size. So if there are not enough samples at the end of last frame, coder adds silence to make frame have necessary size. I also found there chunks like
LAME3.97 (name and version of coder).
So, all we need to do is to get rid of ID3 container. The following solution works for me perfect, no warnings anymore and out file became smaller:
# Length of header that describes ID3 container
ID3_HEADER_SIZE = 10
# Get size of ID3 container.
# Length is stored in 4 bytes, and the 7th bit of every byte is ignored.
#
# Example:
# Hex: 00 00 07 76
# Bin: 00000000 00000000 00000111 01110110
# Real bin: 111 1110110
# Real dec: 1014
#
def get_id3_size(header)
result = 0
str = header[6..9]
# Read 4 size bytes from left to right applying bit mask to exclude 7th bit
# in every byte.
4.times do |i|
result += (str[i].ord & 0x7F) * (2 ** (7 * (3-i)))
end
result
end
def strip_mp3!(raw_mp3)
# 10 bytes that describe ID3 container.
id3_header = raw_mp3[0...ID3_HEADER_SIZE]
id3_size = get_id3_size(id3_header)
# Offset from which mp3 frames start
offset = id3_size + ID3_HEADER_SIZE
# Get rid of ID3 container
raw_mp3.slice!(0...offset)
raw_mp3
end
# Read raw mp3s
hi = File.binread('hi.mp3')
bye = File.binread('bye.mp3')
# Get rid of ID3 tags
strip_mp3!(hi)
strip_mp3!(bye)
# Concatenate mp3 frames
hi << bye
# Save result to disk
File.binwrite('out.mp3', hi)