Pattern target in Makefile not recognized? - makefile

Question

I don't understand why the pattern target %.o: %.cpp ist not recognized by the Makefile below. Line 42 should invoke the rule at line 58.
The purpose is to create a Makefile to generate different executables out of the same code.
Further the Makefile shall (in future) take into account to rebuild the code if header-files were changed (dependencies). But this is no question at this point.
.SECONDEXPANSION:
SUFFIXES += .d
MD := mkdir
MD_FLAGS := -p
RM := rm
RM_FLAGS := -rf
EC := echo
SRC_DIR := src
# SRC_FILES - target specific
OBJ_DIR := obj
# OBJ_FILES - target specific
DEP_DIR := dep
# DEP_FILES - target specific
BUILD_DIR := build
CC := clang++
CC_FLAGS := -c -std=c++11 -I $(SRC_DIR) -O3
LD := clang++
# LD_FLAGS - target specific
.PHONY: all
all: first
.PHONY: first
first: LD_FLAGS :=
first: SRC_FILES :=\
$(SRC_DIR)/executables/first.cpp\
$(SRC_DIR)/factory/milk.cpp
first: obj
first: $(OBJ_FILES)
#echo $(OBJ_FILES)
#echo making $#
first: dep
first: lnk
.PHONY: obj
obj:
$(eval OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES)))
.PHONY: dep
dep:
$(eval DEP_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(DEP_DIR)/%.dep, $(SRC_FILES)))
%.o: %.cpp
#$(EC) "Begin compiling "$#
#$(MD) $(MD_FLAGS) $(dir $#)
#$(CC) $(CC_FLAGS) $< -o $#
#$(EC) "Done compiling "$#
.PHONY: lnk
lnk: $(DEP_FILES) $(OBJ_FILES) $(SRC_FILES)
#$(EC) $(SRC_FILES)
#$(EC) $(OBJ_FILES)
#$(EC) $(DEP_FILES)
#$(EC) "Begin linking "$#
#$(MD) $(MD_FLAGS) $(DEP_DIR) $(BUILD_DIR)
#$(LD) -o $(BUILD_DIR)/$# $(OBJ_FILES) $(LD_FLAGS)
#$(EC) "Done linking "$#
.PHONY: clean
clean:
#$(EC) "Begin cleaning"
#$(RM) $(RM_FLAGS) $(DEP_DIR) $(OBJ_DIR) $(BUILD_DIR)
#$(EC) "Done cleaning"
A snippet of a debug output (make -d) is not a big help I guess but for completion...
Updating goal targets....
Considering target file 'all'.
File 'all' does not exist.
Considering target file 'first'.
File 'first' does not exist.
Considering target file 'obj'.
File 'obj' does not exist.
Finished prerequisites of target file 'obj'.
Must remake target 'obj'.
Successfully remade target file 'obj'.
Considering target file 'dep'.
File 'dep' does not exist.
Finished prerequisites of target file 'dep'.
Must remake target 'dep'.
Successfully remade target file 'dep'.
Considering target file 'lnk'.
File 'lnk' does not exist.
Finished prerequisites of target file 'lnk'.
Must remake target 'lnk'.
Update 1
I've updated the code as it now uses MAKECMDGOALS to build several executables (e.g. first,second) from subsets of a biger set.
No it works as expected but the target all is broken. It's clear to me why but I don't have a solution right now.
.SECONDEXPANSION:
SUFFIXES += .d
MD := mkdir
MD_FLAGS := -p
RM := rm
RM_FLAGS := -rf
EC := echo
SRC_DIR := src
ifeq ($(filter first, $(MAKECMDGOALS)), first)
SRC_FILES :=\
$(SRC_DIR)/executables/first.cpp\
$(SRC_DIR)/factory/milk.cpp
endif
ifeq ($(filter second, $(MAKECMDGOALS)), second)
SRC_FILES :=\
$(SRC_DIR)/executables/second.cpp\
$(SRC_DIR)/factory/milk.cpp\
$(SRC_DIR)/factory/cream.cpp
endif
OBJ_DIR := obj
OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES))
DEP_DIR := dep
DEP_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(DEP_DIR)/%.dep, $(SRC_FILES))
BUILD_DIR := build
CC := clang++
CC_FLAGS := -c -std=c++11 -I $(SRC_DIR) -O3
LD := clang++
ifeq ($(filter first, $(MAKECMDGOALS)), first)
LD_FLAGS :=
endif
ifeq ($(filter second, $(MAKECMDGOALS)), second)
LD_FLAGS :=
endif
.PHONY: all
all: first second
.PHONY: first
first: $(OBJ_FILES) lnk
.PHONY: second
second: $(OBJ_FILES) lnk
%.o: %.cpp
#$(EC) "Begin compiling "$#
#$(MD) $(MD_FLAGS) $(dir $#)
#$(CC) $(CC_FLAGS) $< -o $#
#$(EC) "Done compiling "$#
.PHONY: lnk
lnk: $(OBJ_FILES)
#$(EC) "Begin linking "$#
#$(MD) $(MD_FLAGS) $(DEP_DIR) $(BUILD_DIR)
#$(LD) -o $(BUILD_DIR)/$# $(OBJ_FILES) $(LD_FLAGS)
#$(EC) "Done linking "$#
.PHONY: clean
clean:
#$(EC) "Begin cleaning"
#$(RM) $(RM_FLAGS) $(DEP_DIR) $(OBJ_DIR) $(BUILD_DIR)
#$(EC) "Done cleaning"
Update 2
I had to change the targets first and second, a copy-paste error. Here's the working example:
MD := mkdir
MD_FLAGS := -p
RM := rm
RM_FLAGS := -rf
EC := echo
SRC_DIR := src
ifeq ($(filter first, $(MAKECMDGOALS)), first)
SRC_FILES :=\
$(SRC_DIR)/executables/first.cpp\
$(SRC_DIR)/factories/milk.cpp
endif
ifeq ($(filter second, $(MAKECMDGOALS)), second)
SRC_FILES :=\
$(SRC_DIR)/executables/second.cpp\
$(SRC_DIR)/factories/milk.cpp\
$(SRC_DIR)/factories/cream.cpp
endif
OBJ_DIR := obj
OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES))
DEP_DIR := dep
DEP_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(DEP_DIR)/%.dep, $(SRC_FILES))
BUILD_DIR := build
CC := clang++
CC_FLAGS := -c -std=c++11 -I $(SRC_DIR) -O3
LD := clang++
ifeq ($(filter first, $(MAKECMDGOALS)), first)
LD_FLAGS :=
LD_FILE := first
endif
ifeq ($(filter second, $(MAKECMDGOALS)), second)
LD_FLAGS :=
LD_FILE := second
endif
.PHONY: all
all:
#$(MAKE) $(MAKEFLAGS) first
#$(MAKE) $(MAKEFLAGS) second
.PHONY: first
first: $(OBJ_FILES) lnk
.PHONY: second
second: $(OBJ_FILES) lnk
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
#$(EC) "Begin compiling "$#
#$(MD) $(MD_FLAGS) $(dir $#)
#$(CC) $(CC_FLAGS) $< -o $#
#$(EC) "Done compiling "$#
.PHONY: lnk
lnk: $(OBJ_FILES)
#$(EC) "Begin linking "$(LD_FILE)
#$(MD) $(MD_FLAGS) $(DEP_DIR) $(BUILD_DIR)
#$(LD) -o $(BUILD_DIR)/$(LD_FILE) $(OBJ_FILES) $(LD_FLAGS)
#$(EC) "Done linking "$(LD_FILE)
.PHONY: clean
clean:
#$(EC) "Begin cleaning"
#$(RM) $(RM_FLAGS) $(DEP_DIR) $(OBJ_DIR) $(BUILD_DIR)
#$(EC) "Done cleaning"

Answer 1

You have to understand more clearly make's rules for when variables are expanded. See the GNU make manual section How Make Reads a Makefile for full details.
There you will discover that variables and functions that appear in the target or prerequisites section of a rule definition are expanded immediately as the makefile is parsed. Expansion of variables and functions which appear inside a rule's recipe are deferred until that recipe is invoked.
So let's look at the interesting parts of your makefile:
all: first
first: obj
first: $(OBJ_FILES)
#echo $(OBJ_FILES)
#echo making $#
obj:
$(eval OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES)))
What happens here? Make reads the first line and knows that first is a prerequisite of the default target (because it's the first target in the makefile) all. Then it sees that first depends on the target obj. Then it sees that first depends on the value of the variable $(OBJ_FILES), but at this point OBJ_FILES is not set so it expands to the empty string and doesn't actually depend on any object files.
Now when make gets through parsing things and wants to run the build, it sees the first target is all and that depends on first, which depends on obj, which doesn't depend on anything so it runs the recipe to build the obj target. This uses eval to set the make variable OBJ_FILES so now that has a value, but it's too late to help the prerequisites list of the first target, which has already been computed. So now make runs the recipe for first which prints the value of OBJ_FILES.
You have various other issues here, such as rules (like lnk) which build targets that are not $#.
But, basically you need to reconsider your approach of setting make variables inside recipes. That is useful only in rare/obscure situations. It's not clear to me why you are doing this in a recipe with eval, instead of just assigning OBJ_FILES directly, so I can't advise you specifically how to rewrite your makefile.
If you want to see the set of rules that make parsed for you, you can run make with the -p flag and it will print out the rules database it's using to build your project.