I have a project that is structured with a main directory (project) and a subdirectory (add) in that main directory.
I want to run a makefile in the main directory, project, which calls another makefile in the 'add' subdirectory.
However, the makefile only works correctly if I call it from the subdirectory manually. If I run $(MAKE) -C add, preprocessor warnings are triggered and the file does not compile. If I run the makefile manually in the subdirectory, the compilation goes fine (as it should. I do not why the warnings are being triggered if I use the makefile from the outside directory).
How can I fix this so that the makefile is called correctly?
Related
Both Makefile and makefile.linux exists in the source code directory which I want to compile, and it seems make command fetches makefile.linux for compiling the source code. May I know how makefile.linux is being used for compilation?
I have an external out-of-tree linux kernel module, say foo. Therein, I have a directory include/uapi/ that should, I assume, contain Kbuild file defining inclusion rules and/or headers to export. The directory include/uapi/ on its turn contains one more directory linux having the target user-API headers in, say three files foo.h bar.h baz.h
Ok, I have defined this Kbuild file inside include/uapi and it contains:
header-y += linux/
Then, inside include/uapi/linux directory I've defined one more KBuild and it has the content:
header-y += foo.h bar.h baz.h
Now I am expecting that upon running the command
make -C /lib/modules/5.4.48-dannftk/build M=/home/dannftk/foo INSTALL_HDR_PATH=/home/dannftk/my_exported_headers/ headers_install
I will get the headers installed in the /home/dannftk/my_exported_headers/ directory, instead, I am getting the error saying:
make: *** No rule to make target 'headers_install'. Stop.
/home/dannftk/foo - the path the out-of-tree module discussed is located by
/lib/modules/5.4.48-dannftk/build - the build directory of the kernel, it points to /usr/src/linux-5.4.48 containing the source code of the kernel, actually, I am on Gentoo Linux
May someone give me a hint what I am doing wrongly? Am I incorrectly setting rules for Kbuild? Or maybe I am locating them in unexpected for the kernel build system directories?
Thank you in advance
I personally consider this issue as a bad Kbuild error message. It's too confusing.
The answer is in linux documentation:
--- 2.3 Targets
When building an external module, only a subset of the "make"
targets are available.
make -C $KDIR M=$PWD [target]
The default will build the module(s) located in the current
directory, so a target does not need to be specified. All
output files will also be generated in this directory. No
attempts are made to update the kernel source, and it is a
precondition that a successful "make" has been executed for the
kernel.
modules
The default target for external modules. It has the
same functionality as if no target was specified. See
description above.
modules_install
Install the external module(s). The default location is
/lib/modules/<kernel_release>/extra/, but a prefix may
be added with INSTALL_MOD_PATH (discussed in section 5).
clean
Remove all generated files in the module directory only.
help
List the available targets for external modules.
There were some hacks available in older kernel versions, as adding header-y += ... into Kbuild file, but, as you see, it's not the official approach.
Looks like developers of out-of-tree modules should take care of headers installation manually, without reusing of linux kernel make rules.
I want to automatically create Makefile dependency files in a hidden folder but I can't find an example of how to create dependency files automatically. Everything concerning makefile is gcc, but I am using not for gcc and I am not too familiar with gcc.
I have a makefile like this.
importf = .mkfiles/import
import: $(importf)
$(importf):
#$(call make_function,0,import)
Could you please help me what I am missing in the makefile.
I installed OMNET++ 5.1 on my Ubuntu 16 OS and imported my project into the Eclipse IDE. But I can not compile my project as before. Make is giving me error:
make1: *** No rule to make target 'msgheaders'. Stop.
I have a folder called loggingWindow that has its own custom makefile and is excluded from the source.
But I noticed that the generated makefile is not correct:
The makefile is calling msgheaders and smheaders targets in the logginWindow folder. The loggingWindow is a completely separate application with its own makefile and has no idea about mshheader!
Also make clean does not work!
The clean window stuck without any progress:
As a temporary workaround, I have added phony targets (msgheaders, smheaders) in order to compile my project.
As a workaround you can add these targets to your own Makefile in logginWindow, for example:
msgheaders:
echo Do nothing
smheaders:
make all
# content from your existing Makefile
all:
...
I have a situation where I've refactored some code, and moved an include file.
Attempting to build the source tree yields an error:
make: *** No rule to make target `cmd/dispatcher.h', \
needed by `/tmp/test/dispatcher/main.o'. Stop.
If I do a make clean (which removes the outdated main.o file), and then rebuild I get a different error:
...src/test/dispatcher/main.cpp:3:28: fatal error: cmd/dispatcher.h: \
No such file or directory
Question:
Is there any way to invalidate main.o when one of its dependencies is missing?
There's no magic in make. If main.o depends on dispatcher.h, then it is written somewhere.
I suspect your Makefile runs gcc with the -MD or -MDD option that creates a dependency file. Usually they are named with a .d suffix. These dependencies files are automatically created by gcc as Makefile content: target: dependencies.
These files are then included into the main Makefile to provide the full automagic dependencies.
You should look for these .d files and remove them.