I am working in Android source code with Kitkat version, and I encounter a weird problem when I executing make command, the error message are listed below.
make: No rule to make target `out/target/product/msm8909_512/obj/STATIC_LIBRARIES/revlib_intermediates/export_includes',
needed by `out/target/product/msm8909_512/obj/STATIC_LIBRARIES/third_party_harfbuzz_ng_harfbuzz_ng_gyp_intermediates/import_includes'.
Stop.make: Waiting for unfinished jobs....
I can't find a proper answer so far, do I need to install any additional libraries ?
Env: ubuntu 12.04 && java version 1.6.0_45
Please do me a favor.
No rule to make target xxx, needed by yyy.
This means that make decided it needed to build a target, but then couldn't find any instructions in the makefile on how to do that, either explicit or implicit (including in the default rules database). If you want that file to be built, you will need to add a rule to your makefile describing how that target can be built. Other possible sources of this problem are typos in the makefile (if that filename is wrong) or a corrupted source tree (if that file is not supposed to be built, but rather only a prerequisite).
reference
Related
In Xcode, I have a project where one of the targets is using an external build system (Make).
When I select Product → Build Documentation, it fails on the Make target, since it’s trying to run make docbuild and have no such target in my makefile:
make: *** No rule to make target `docbuild'. Stop.
Command ExternalBuildToolExecution failed with a nonzero exit code
I can’t seem to find a way to disable this for only this target. Can someone tell me how to do this, please?
I am trying to run a code on Eclipse in C, however I keep getting the same Error in my make file. I have read similar blogposts, but i can't seem to solve my problem. I am relatively new to programming and not sure what the problem is.
Here is a copy of my makefile:
#CCE_Board_Definitions:BMI085;BMI088
COINES_INSTALL_PATH ?= ../../../..
EXAMPLE_FILE ?= bmi08x_read_sensor_data.c
SHUTTLE_BOARD ?= BMI085
include $(COINES_INSTALL_PATH)/examples/examples.mk
When i try to run my code I get the following error:
mingw32-make all
mingw32-make: *** No rule to make target 'all'. Stop.
"mingw32-make all" terminated with exit code 2. Build might be incomplete.
In Properties I have renamed the build command to "mingw32-make" (because I was told to do so in the guide for this code).
Can anyone think of what the problem might be?
Thank you in advance :)
Samboff
I installed OMNET++ 5.1 on my Ubuntu 16 OS and imported my project into the Eclipse IDE. But I can not compile my project as before. Make is giving me error:
make1: *** No rule to make target 'msgheaders'. Stop.
I have a folder called loggingWindow that has its own custom makefile and is excluded from the source.
But I noticed that the generated makefile is not correct:
The makefile is calling msgheaders and smheaders targets in the logginWindow folder. The loggingWindow is a completely separate application with its own makefile and has no idea about mshheader!
Also make clean does not work!
The clean window stuck without any progress:
As a temporary workaround, I have added phony targets (msgheaders, smheaders) in order to compile my project.
As a workaround you can add these targets to your own Makefile in logginWindow, for example:
msgheaders:
echo Do nothing
smheaders:
make all
# content from your existing Makefile
all:
...
I am having some trouble to compile GCC. When I try to compile it, this error appears:
Makefile:26: *** missing separator. Stop.
The line 26 refers to the first line of this condition:
#if gcc
ifeq (,$(.VARIABLES)) # The variable .VARIABLES, new with 3.80, is never empty.
$(error GNU make version 3.80 or newer is required.)
endif
#endif gcc
I already tried to insert a TAB between the keywords but it didn't work. The only thing I tried and seems to work is to change the condition to:
ifeq ($(gcc),)
ifeq (,$(.VARIABLES)) # The variable .VARIABLES, new with 3.80, is never empty.
$(error GNU make version 3.80 or newer is required.)
endif
endif
Informations:
Make log: http://pastebin.com/t5eNYJd5
Make log (after changing the condition): http://pastebin.com/HHjQKdDx
My make version is: 4.0.
GCC version I am trying to build: 5.2.0
I am using fedora 22.
I've got a workaround. The problem is that the Makefile contains hundreds of '#if', therefore, I would like to know why is it using '#if' if they do not work ?
Thanks in advance.
I stumbled upon this same problem. This question is a little old and it looks like you found a workaround, but I'll document my findings here as well for the People of the Future.
Background
GCC currently requires you to perform an out-of-source build. Based on the commands shown, some of the documentation and online QA implies that this is valid:
svn checkout svn://gcc.gnu.org/svn/gcc/trunk gcc;
gcc/configure <configure options>;
make -j 8 && make install;
This nests the source directory in the build directory, but I would expect that to count as "out-of-source." Running without -j 8 still produced the problem. I did this on a RHEL6 system, using GNU make 4.2. I was attempting to build GCC 8.0.0.
Solution
I found that making the source and build directories adjacent rather than creating builddir/sourcedir resolved the problem.
Additional info
Here's are relevant snippets from the GCC build instructions:
We use srcdir to refer to the toplevel source directory for GCC; we use objdir to refer to the toplevel build/object directory.
...
If you obtained the sources via SVN, srcdir must refer to the top gcc directory, the one where the MAINTAINERS file can be found, and not its gcc subdirectory, otherwise the build will fail.
...
First, we highly recommend that GCC be built into a separate directory from the sources which does not reside within the source tree. This is how we generally build GCC; building where srcdir == objdir should still work, but doesn’t get extensive testing; building where objdir is a subdirectory of srcdir is unsupported.
Depending on your definition of "source tree", these instructions may or may not proscribe building the way I first attempted. They should probably be updated to clarify this case.
As to the specific reason that Makefile won't run, that snippet is not valid make syntax - if is not a make keyword, and referenced variables must be enclosed like so: $(varname). # simply prevents the command from being echoed.
Rather, this is supposed to be multiline interpolated bash. This StackOverflow answer shows this being done in a Makefile, but it's done as part of a recipe. I see no evidence that this is valid as a standalone entity.
In the correctly-generated Makefile, the section you posted is absent, and all interpolated bash appears in a recipe.
On a Leopard Mac mini (PowerPC) I'm trying to compile Apple-GCC-3.3 which I got from https://opensource.apple.com/tarballs/gcc_os/gcc_os-1819.tar.gz
./configure gets completed w.o. any error but make gives the following errors:
When input only "make" it says
make: *** No rule to make target `all', needed by `default'. Stop.
When input make -f Makefile, the make starts fine but somewhere halfway down the process it stops with:
gcc tclAppInit.o -L/Users/macmini/Downloads/gcc_os-1819/tcl/unix -ltcl8.0 -lc \-o tclsh
make[1]: *** No rule to make target `all'. Stop.
make: *** [all-expect] Error 2
For this type of error, it's said that the tar might be dropping long filenames during the untar operation but I tried with different versions of tar such as 1.14, 1.27 and the error is the same.
What should I do? Thanks.
!(http://i.hizliresim.com/Kl9rRJ.png)
(Just in case you may wonder why I want to compile GCC-3.3, it's because it's needed to compile GIMP on PowerPC Macs)
Problem solved. It turned really hard to compile GCC-3.3 from source, so I made it easy and installed it from XCode 3.1 DVD, under the Packages directory where GCC-3.3.pkg was present.
Now the GIMP can be compiled.
Summary: It's a good idea to install the Apple's compiler group of programs from the XCode DVD.
Thanks.