I'm brand new to VHDL and the Quartus design environment, and I'm trying to run the simulation of some textio but I must be missing something... When I compile the following code (which I borrowed snippets of from an OSU VHDL textio guide (http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/text_io.pdf), I get error 10533:
Error (10533): VHDL Wait Statement error at tio_top.vhd(36): Wait Statement must contain condition clause with UNTIL keyword
What type of condition is appropriate to use in this scenario? I've tried creating a condition that evaluates to a constant true or false, but that gives an error also.
Perhaps my understanding of process is wrong and it needs to continuously run?
Basically I just want to output variable a to a text file... Do I need to create a testbench?
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.math_complex.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tio_top is
end tio_top;
architecture main of tio_top is
begin
-----------------------------------------------------------------------------
--practice with textio
file_io: --declare a process for executing file input/output
process is
file out_file : text open read_mode is "out_values"; --declare output file name
variable out_line : line; --declare variable of type line to store values
variable a : std_logic; --declare other logic varialbes for playing around with
begin --put the meet of the textio here
a := '1';
write(out_line,a);
writeline(out_file, out_line);
wait; --allows simulation to halt!
end process;
end main;
Related
I tried to run some code from Stack Overflow (How to write an integer to stdout as hexadecimal in VHDL?) and it turned out that to_hstring doesn't work (Even though std library is standard for VHDL). I am using Active-HDL 9.1 (probably the root of the problem is in the old version of Active-HDL). I'm new to VHDL coding, so I believe I missed something obvious there. Thanks for any help!
Here is the sample code:
library ieee,std;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity min is
end min;
architecture behav of min is
begin
process is
begin
report "i = 0x" & to_hstring(to_signed(16, 32));
end process;
end behav;
And output of the compiler:
While writing the question, I read again (How to write an integer to stdout as hexadecimal in VHDL?) and found that was mentioned VHDL-2008. After that I checked my compile command (automatically generated by Active-HDL) it turned out that VHDL-2002 is the default for compilation command:
After changing the parameter to -2008, everything worked:
Below is part of the
help acom
output
And the output of the program execution:
I have written this simple code. But when i try to simulate it using Modelsim, it shows the an error saying library cannot be mapped. How do i sort it?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity p1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end p1;
architecture Behavioral of p1 is
begin
c <= a or b;
end Behavioral;
This is the error:
ERROR: Failed to map the library
probably you changed directory, and library work is not created there, although a mapping exists in your modelsim.ini.
Type in transcript:
vlib work
To create the library work.
edit: if the mapping is also missing (i.e. the above solution does not solve this) add the following command:
vmap work work
P.s. Stupid thing is: modelsim should not default to a library named "work", as "work" is a reserved keyword (meaning 'the current library'). But ignore that, as that has been an issue/bug for tens of years now...
I have a verilog module from an external vendor. I would like to wrap it in VHDL.
The problem is that the verilog module contains identifiers that have adjacent underscores in their names. VHDL seems not to allow this. Surely I can wrap the verilog module into another verilog module and then wrap it into a VHDL module, but isn't there a way to avoid it?
I wrote a small example to illustrate:
Verilog:
module underscore (
test__in,
test__out
);
input test__in;
output test__out;
assign test__out = test__in;
endmodule
VHDL:
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_underscore is
end entity;
architecture rtl of tb_underscore is
signal test_in: std_logic;
signal test_out: std_logic;
begin
i_underscore: entity work.underscore port map (
test__in => test_in,
test__out => test_out
);
end architecture;
The VHDL code does not compile because of the adjacent underscores.
I'd like to understand the syntax used in the line of code below where an alternate name is created using an ALIAS declaration. Specifically, I'd like to know what the << and >> imply. An example alias statement is,
alias x2_dac_data is
<< signal server.x2_dac_data : std_logic_vector(23 downto 0) >>;
where server is an instantiated component and x2_dac_data is a signal with the component, but not listed in the port declaration.
I've reviewed Pedroni's text and a course guide, neither of which reference the << ... >> syntax as it relates to alias.
Thanks
The double Less-Thans and double Greater characters (<<, >>) enclose an External Name, which is a path name to a object (e.g. signal, constant, variable) through a design model's hierarchy. The intended use is for design verification, allowing a testbench to reach objects not visible at the top level of a design.
See Peter Ashenden and Jim Lewis The Designer's Guide to VHDL (3rd Ed.), Section 18.1 External Names and Doulos VHDL-2008: Easier to use, Hierarchical Names, or IEEE Std 1076-2008, 8.7 External names.
There's an example on Page 561 of The Designer's Guide to VHDL:
alias duv_data_bus is
<<signal .tb.duv_rtl.data_bus : std_ulogic_vector(0 to 15)>>;
The syntax is described on Page 560. Pages 559-562 are visible in the Google Book preview. The example found in The Designer's Guide to VHDL dealing with external names is also found in Chapter 2, Section 2.1 External Names of VHDL 2008 Just the New Stuff by the same authors and while without the EBNF syntax description goes further into the philosophy behind external names. Unfortunately the book's Google Book preview doesn't reach Section 2.1. Jim Lewis is organizing the P1076 Study Group of the IEEE VHDL Analysis and Standardization Group (VASG) responsible for developing the next revision of IEEE Std 1076-201X. Peter Ashenden is a long time contributor to the VHDL standardization effort as well.
A better solution than aliases to hierarchical signal references in packages: using a package to share signals between bfm-procedures and testbench toplevel. Example:
library ieee;
use ieee.std_logic_1164.all;
--VHDL 2008 with questasim
package bfm is
signal tb_ii_a : std_logic;
signal tb_ii_b : std_logic;
signal tb_oo_c : std_logic;
procedure wiggle;
end package;
package body bfm is
procedure wiggle;
begin
tb_oo_c <= force in '1';
wait for 10 ns;
tb_oo_c <= force in '0';
wait for 10 ns;
tb_oo_c <= force in tb_ii_a and tb_ii_b;
end procedure;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use std.env.all;
library work;
use work.bfm.all;
entity tb;
end tb;
architecture tb_dut1 of tb is
begin
dut : entity work.dut port map(
oo_a => tb_ii_a, -- output of dut input of tb bfm
oo_b => tb_ii_b, -- output of dut input of tb bfm
ii_c => tb_oo_c -- input of dut output of tb bfm
);
testcase : process
begin
wiggle;
wait for 100 ns;
std.env.stop(0);
end process;
end architecture;
I've a problem with some VHDL syntax in some old code that I want to reuse. It is accepted by the synthesis tool (Synplify) but the simulator (Aldec Active-HDL 8.3) gives the following error. (Note: This construction was accepted by a previous version of this simulator).
#Error: COMP96_0228: buffered_data.vhdl : (19, 28): The actual must be denoted by a static signal name, if the actual is associated with a signal parameter of any mode.
I get that the error doesn't like the (i) in the signal clk(i) but I don't want to unroll the loop to (0),(1),etc because it's used in several different configurations for different port sizes and I'm sure there must be a way to describe this.
My solution so far is to encapsulate one instance in it's own entity/arch hierarchy and use a "generate" to instantiate once for each port but I don't like it. Any better ideas?
Very simplified example showing exactly my issue. (The intent is to ensure that data is first clocked into the FPGA using its own associated clock before anything else)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity input_buffer is
port(
clk : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end input_buffer;
architecture rtl of input_buffer is
constant c_NumOfPorts : integer := 3;
begin
p_process: process(clk)
begin
for i in 0 to c_NumOfPorts-1 loop
if rising_edge(clk(i)) then -- error here
data_out(i) <= data_in(i);
end if;
end loop;
end process;
end rtl;
If you change the loop inside the process into a generate statement outside the process, it works fine in ModelSim (I don't have Aldec available), and IMHO seems cleaner than a single process with a bunch of clocks. I would also typically use a generic to define the port widths, rather than pulling them in as a constant inside the architecture, but I figure you've got some reason for doing it that way:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity input_buffer is
port(
clk : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end input_buffer;
architecture rtl of input_buffer is
constant c_NumOfPorts : integer := 3;
begin
gen : for i in 0 to c_NumOfPorts-1 generate
begin
p_process: process(clk(i))
begin
if rising_edge(clk(i)) then -- error here
data_out(i) <= data_in(i);
end if;
end process;
end generate;
end rtl;
FWIW, I get the same with Modelsim:
Model Technology ModelSim PE vcom 10.0a Compiler 2011.02 Feb 20 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity input_buffer
-- Compiling architecture rtl of input_buffer
** Error: clk.vhd(19): (vcom-1450) Actual (indexed name) for formal "s" is not a static signal name.
** Error: clk.vhd(25): VHDL Compiler exiting
As an aside - is there a reason for your use of the constant and not just doing this?
for i in clk'range loop
But no actual answer has occurred to me yet, sorry!