Manage exit code in Makefile define - makefile

Question

I am creating a target that can be used as a hook to add some extra procedure when is needed.
This is the code in the main Makefile
export MSG:="Linux hook"
linux-build:
# echo "Dependency target"
linux-build-post: linux-build
# make -s -f linux.hook -q linux_build_post 2> /dev/null ; \
if [ $$? -le 1 ] ; then \
echo "Target exist" ; \
make -s -f linux.hook linux_build_post ; \
else \
echo "Target doesn't exist" ; \
fi
# touch $#
This is the code in the file linux.hook
linux_build_post:
# echo ${MSG}
This code works correctly, but now I am trying to create a template in the main Makefile. For example:
export MSG:="Linux hook"
linux-build:
# echo "Dependency target"
# Common hook target
# Parameters:
# 1: Target name
# 2: Dependecies
# 3: Hook name
define COMMON_HOOK_TARGET
$(1): $(2)
make -s -f $(3).hook -q $(1) 2> /dev/null ; \
if [ $$? -le 1 ] ; then \
echo "Target exist" ; \
make -s -f $(3).hook $(1) ; \
else \
echo "Target doesn't exist" ; \
fi
touch $(1)
endef
$(eval $(call COMMON_HOOK_TARGET,linux-build-post,linux-build))
But in this case the make command fails because $$? is replaced with the dependency linux-build then the if condition is evaluated like this if [ linux-build -le 1 ].
Error reported:
/bin/sh: 1: [: Illegal number: linux-build
How I can change the code in order to use $$? as the exit code of the previous command make -s -f $(3).hook -q $(1) 2> /dev/null ?

Answer 1

I think the answer is actually this:
if [ $$$$? -le 1 ] ; ...
The call to call turns "$$$$" into "$$", then when Make executes the rule it converts "$$?" to "$?" and passes it to the shell.