Incompatibile Slices in VHDL - vhdl

Question

I am learning VHDL and for first project I picked up simple Brainfuck processor. When I try to compile it, I get error about incompatibile slices. I am using EdWinXP. How do I fix my code? Are there many mistakes in my code? Is there alternative of VHDL that would be simpler for C programmer?
use ieee.std_logic_1164.all;
entity BFCPU is
port (
I0 : in std_logic; --INPUT
I1 : in std_logic; --PROGRAM
I2 : in std_logic; --PROGRAM READY
O1 : out std_logic; --PROGRAM NEEDED
O2 : out std_logic; --OUTPUT
O3 : out std_logic; --OUTPUT WRITTEN
O4 : out std_logic); --INPUT NEEDED
--O5 : out std_logic); --INPUT POOLING CLOCK
end BFCPU;
architecture work of BFCPU is
type t_Memory is array (0 to 127) of std_logic_vector(7 downto 0);
signal rammem : t_Memory;
signal pointer : std_logic;
begin
pointer <= 0;
workflow: process (I2) is
begin
if I1=1 then
rammem(pointer) <= std_logic_vector(unsigned(rammem(pointer)) + 1);
elsif I1=2 then
rammem(pointer) <= std_logic_vector(unsigned(rammem(pointer)) - 1);
elsif I1=3 then
pointer <= pointer - 1;
elsif I1=4 then
pointer <= pointer + 1;
elsif I1=5 then
O2 <= rammem(pointer);
elsif I1=6 then
O4 <= not O4;
inwait: while( I0 = 0 ) loop
if not (I0 = 0) then
rammem(pointer) <= I0;
end if;
end loop inwait;
O4 <= not O4;
end if;
end process workflow;
end work;

Answer 1

What you're writing below the begin statement and outside a process is always true, so this isn't sequential in any form. Imagine like an FPGA pin, which is soldered to ground.
You try to manipulate the pointer signal from within a process, but you can't because your pointer is fixed to '0'.
If you want the pointer initializing to '0', as it looks like, you have to put this line within the process. However, i see you try to call arithmetic operations with the pointer signal, but you are defining the signal as std_logic. std_logic can represent '0', '1' and several other states, like High-Z, but not a number. You should take an integer or natural for calculations.