I would like to create a Master Makefile from which I go to subdirectories and call other Makefiles. For this master Makefile, I did :
DIR_1D = $(dir $(mkfile_dir))1D
DIR_2D = $(dir $(mkfile_dir))2D
DIR_3D = $(dir $(mkfile_dir))3D
# Phony target
.PHONY: all clean
all:
#(cd $(DIR_1D) ; $(MAKE))
#(cd $(DIR_2D) ; $(MAKE))
#(cd $(DIR_3D) ; $(MAKE))
# Clean target
clean:
#(cd $(DIR_1D) ; $(MAKE) $#)
#(cd $(DIR_2D) ; $(MAKE) $#)
#(cd $(DIR_3D) ; $(MAKE) $#)
UPDATE : Sorry, stupid typo error, fixed, thanks
You set variables DIR_1D, DIR_2D, DIR_3D, but your cd commands use DIR_1, DIR_2, DIR_3. Since you didn't set those variables, you're running cd with no arguments, and cd with no arguments means cd "$HOME".
Related
I'm getting the following output from the console when trying to run make.
==== Building Project (debug) ====
process_begin: CreateProcess(NULL, echo Creating obj/Debug, ...) failed.
make (e=2): The system cannot find the file specified.
make[1]: *** [Project.make:90: obj/Debug] Error 2
make: *** [Makefile:30: Project] Error 2
The makefile is generated using premake and I have no experience with makefiles. the make file looks like this:
# Alternative GNU Make workspace makefile autogenerated by Premake
ifndef config
config=debug
endif
ifndef verbose
SILENT = #
endif
ifeq ($(config),debug)
Project_config = debug
else ifeq ($(config),release)
Project_config = release
else
$(error "invalid configuration $(config)")
endif
PROJECTS := Project
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
Project:
ifneq (,$(Project_config))
#echo "==== Building Project ($(Project_config)) ===="
#${MAKE} --no-print-directory -C . -f Project.make config=$(Project_config)
endif
clean:
#${MAKE} --no-print-directory -C . -f Project.make clean
help:
#echo "Usage: make [config=name] [target]"
#echo ""
#echo "CONFIGURATIONS:"
#echo " debug"
#echo " release"
#echo ""
#echo "TARGETS:"
#echo " all (default)"
#echo " clean"
#echo " Project"
#echo ""
#echo "For more information, see https://github.com/premake/premake-core/wiki"
and the premake5.lua file is this:
workspace "Workspace"
configurations { "Debug", "Release" }
project "Project"
kind "ConsoleApp"
language "C++"
targetdir "bin/%{cfg.buildcfg}"
files { "**.h", "**.cpp" }
filter "configurations:Debug"
defines { "DEBUG" }
symbols "On"
filter "configurations:Release"
defines { "NDEBUG" }
optimize "On"
Any ideas on what might be wrong?
Thanks in advance.
Edit: the Project.make file looks like this:
# Alternative GNU Make project makefile autogenerated by Premake
ifndef config
config=debug
endif
ifndef verbose
SILENT = #
endif
.PHONY: clean prebuild
SHELLTYPE := posix
ifeq (.exe,$(findstring .exe,$(ComSpec)))
SHELLTYPE := msdos
endif
# Configurations
# #############################################
RESCOMP = windres
INCLUDES +=
FORCE_INCLUDE +=
ALL_CPPFLAGS += $(CPPFLAGS) -MMD -MP $(DEFINES) $(INCLUDES)
ALL_RESFLAGS += $(RESFLAGS) $(DEFINES) $(INCLUDES)
LIBS +=
LDDEPS +=
LINKCMD = $(CXX) -o "$#" $(OBJECTS) $(RESOURCES) $(ALL_LDFLAGS) $(LIBS)
define PREBUILDCMDS
endef
define PRELINKCMDS
endef
define POSTBUILDCMDS
endef
ifeq ($(config),debug)
TARGETDIR = bin/Debug
TARGET = $(TARGETDIR)/Project.exe
OBJDIR = obj/Debug
DEFINES += -DDEBUG
ALL_CFLAGS += $(CFLAGS) $(ALL_CPPFLAGS) -g
ALL_CXXFLAGS += $(CXXFLAGS) $(ALL_CPPFLAGS) -g
ALL_LDFLAGS += $(LDFLAGS)
else ifeq ($(config),release)
TARGETDIR = bin/Release
TARGET = $(TARGETDIR)/Project.exe
OBJDIR = obj/Release
DEFINES += -DNDEBUG
ALL_CFLAGS += $(CFLAGS) $(ALL_CPPFLAGS) -O2
ALL_CXXFLAGS += $(CXXFLAGS) $(ALL_CPPFLAGS) -O2
ALL_LDFLAGS += $(LDFLAGS) -s
endif
# Per File Configurations
# #############################################
# File sets
# #############################################
GENERATED :=
OBJECTS :=
GENERATED += $(OBJDIR)/main.o
OBJECTS += $(OBJDIR)/main.o
# Rules
# #############################################
all: $(TARGET)
#:
$(TARGET): $(GENERATED) $(OBJECTS) $(LDDEPS) | $(TARGETDIR)
$(PRELINKCMDS)
#echo Linking Project
$(SILENT) $(LINKCMD)
$(POSTBUILDCMDS)
$(TARGETDIR):
#echo Creating $(TARGETDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) mkdir -p $(TARGETDIR)
else
$(SILENT) mkdir $(subst /,\\,$(TARGETDIR))
endif
$(OBJDIR):
#echo Creating $(OBJDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) mkdir -p $(OBJDIR)
else
$(SILENT) mkdir $(subst /,\\,$(OBJDIR))
endif
clean:
#echo Cleaning Project
ifeq (posix,$(SHELLTYPE))
$(SILENT) rm -f $(TARGET)
$(SILENT) rm -rf $(GENERATED)
$(SILENT) rm -rf $(OBJDIR)
else
$(SILENT) if exist $(subst /,\\,$(TARGET)) del $(subst /,\\,$(TARGET))
$(SILENT) if exist $(subst /,\\,$(GENERATED)) rmdir /s /q $(subst /,\\,$(GENERATED))
$(SILENT) if exist $(subst /,\\,$(OBJDIR)) rmdir /s /q $(subst /,\\,$(OBJDIR))
endif
prebuild: | $(OBJDIR)
$(PREBUILDCMDS)
ifneq (,$(PCH))
$(OBJECTS): $(GCH) | $(PCH_PLACEHOLDER)
$(GCH): $(PCH) | prebuild
#echo $(notdir $<)
$(SILENT) $(CXX) -x c++-header $(ALL_CXXFLAGS) -o "$#" -MF "$(#:%.gch=%.d)" -c "$<"
$(PCH_PLACEHOLDER): $(GCH) | $(OBJDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) touch "$#"
else
$(SILENT) echo $null >> "$#"
endif
else
$(OBJECTS): | prebuild
endif
# File Rules
# #############################################
$(OBJDIR)/main.o: main.cpp
#echo $(notdir $<)
$(SILENT) $(CXX) $(ALL_CXXFLAGS) $(FORCE_INCLUDE) -o "$#" -MF "$(#:%.o=%.d)" -c "$<"
-include $(OBJECTS:%.o=%.d)
ifneq (,$(PCH))
-include $(PCH_PLACEHOLDER).d
endif
The error message appears to be associated with this rule from Project.make ...
$(OBJDIR):
#echo Creating $(OBJDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) mkdir -p $(OBJDIR)
else
$(SILENT) mkdir $(subst /,\\,$(OBJDIR))
endif
... and I infer from the appearance of CreateProcess in the diagnbostic message that you are trying to perform this build on Windows.
The issue is a failure to create a subdirectory obj/Debug of the working directory. Sometimes such diagnostics are misleading as to the specific nature of the problem, but here are some possibilities:
the Windows branch of the implicated rule appears to be relying on "command extensions" to be enabled in order to create two directories with one mkdir command. They are enabled by default, but they can be disabled either globally or on a per-processes basis. If they are disabled at least for the cmd.exe process in which you are performing your build then the failure you describe is likely. In that case, you could probably work around that particular issue by manually creating the obj directory, but you might face other, similar ones.
Alternatively, you may simply not be authorized to write in the project folder.
I'm working on an advanced makefile that I found in a book. I've got some simple rules inside:
clean to delete binaries
fclean to delete some extra files too (links to binaries generated by ln)
all to make all
re to make fclean then make all
when I do make fclean then make all, it works perfectly. When i do make re, an error occurs:
error: unable to open output file '/Users/malberte/work/libft/bin/libft/common/ft_atoi.o':
'No such file or directory'
1 error generated.
So here is my code:
$(_MODULE_NAME)_OBJS := $(addsuffix $(_OBJEXT),$(addprefix $($(_MODULE_NAME)_OUTPUT)/,$(basename $(SRCS)))) $(DEPS)
$(_MODULE_NAME)_BINARY := $($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(BINARY_EXT)
$(_MODULE_NAME)_EXPOSE_BINARY := $(_ROOT)/$(BINARY)$(BINARY_EXT)
ifneq ($(_NO_RULES),T)
ifneq ($($(_MODULE_NAME)_DEFINED), T)
_CLEAN := clean-$(_MODULE_NAME)
_FCLEAN := fclean-$(_MODULE_NAME)
_ALL := all-$(_MODULE_NAME)
_RE := re-$(_MODULE_NAME)
_IGNORE := $(shell mkdir -p $($(_MODULE_NAME)_OUTPUT))
.PHONY: all re $(_ALL) $(_RE)
re: fclean all
# re: $(_RE)
# $(_RE): $(_FCLEAN) $(_ALL)
all: $(_ALL)
$(_ALL): $($(_MODULE_NAME)_BINARY)
.PHONY: $(_MODULE_NAME)
$(_MODULE_NAME): $($(_MODULE_NAME)_BINARY)
.PHONY: fclean clean $(_CLEAN)
fclean: $(_FCLEAN)
$(_FCLEAN): $(_CLEAN)
rm -rf $($(patsubst fclean-%,%,$#)_EXPOSE_BINARY)
clean: $(_CLEAN)
$(_CLEAN):
rm -rf $($(patsubst clean-%,%,$#)_OUTPUT)
$($(_MODULE_NAME)_OUTPUT)/%.o: $(_MODULE_PATH)/%.c
#$(COMPILE.c) -o '$#' '$<'
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_LIBEXT): $($(_MODULE_NAME)_OBJS)
#if [ "$(LIBMERGE)" = "F" ]; \
then \
$(AR) r '$#' $^; \
ranlib '$#'; \
else \
libtool -static -o '$#' $^; \
fi
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_EXEEXT): $($(_MODULE_NAME)_OBJS)
$(LINK.c) $^ -o '$#'
$(_MODULE_NAME)_DEFINED := T
endif
endif
I've tried lot of things, I really don't understand what is happening when I use make re and it throws the error above.
Someone has an idea please ?
You have this line in your makefile:
_IGNORE := $(shell mkdir -p $($(_MODULE_NAME)_OUTPUT))
which creates the output directory, as the makefile is being parsed. Then you run your clean target which invokes this recipe:
rm -rf $($(patsubst clean-%,%,$#)_OUTPUT)
which causes the output directory to be deleted. Then you run your all target which invokes the compiler and asks it to write the output file to $($(_MODULE_NAME)_OUTPUT)/%.o but that directory no longer exists.
So the compiler gives you the error:
error: unable to open output file '...': No such file or directory
If you run make twice, then the first time you clean and delete the directory, then when you run make all it will run the _IGNORE shell command and create the directory again so it will exist.
If you run make re one time, then the makefile is only parsed one time and the output directory is only created one time (before it's deleted).
Okay thank you so much. It drove me to think about how a makefile really works, so here is my basic solution, thanks to you:
$(_MODULE_NAME)_OBJS := $(addsuffix $(_OBJEXT),$(addprefix $($(_MODULE_NAME)_OUTPUT)/,$(basename $(SRCS)))) $(DEPS)
$(_MODULE_NAME)_BINARY := $($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(BINARY_EXT)
$(_MODULE_NAME)_EXPOSE_BINARY := $(_ROOT)/$(BINARY)$(BINARY_EXT)
ifneq ($(_NO_RULES),T)
ifneq ($($(_MODULE_NAME)_DEFINED), T)
_OUTPUT_TREE := output-tree-$(_MODULE_NAME)
_CLEAN := clean-$(_MODULE_NAME)
_FCLEAN := fclean-$(_MODULE_NAME)
_ALL := all-$(_MODULE_NAME)
_RE := re-$(_MODULE_NAME)
# _IGNORE := $(shell mkdir -p $($(_MODULE_NAME)_OUTPUT))
.PHONY: all re $(_ALL) $(_RE)
re: fclean all
# re: $(_RE)
# $(_RE): $(_FCLEAN) $(_ALL)
all: $(_ALL)
$(_ALL): $($(_MODULE_NAME)_BINARY)
.PHONY: $(_MODULE_NAME)
$(_MODULE_NAME): $($(_MODULE_NAME)_BINARY)
.PHONY: fclean clean $(_CLEAN)
fclean: $(_FCLEAN)
$(_FCLEAN): $(_CLEAN)
rm -rf $($(patsubst fclean-%,%,$#)_EXPOSE_BINARY)
clean: $(_CLEAN)
$(_CLEAN):
rm -rf $($(patsubst clean-%,%,$#)_OUTPUT)
$($(_MODULE_NAME)_OUTPUT)/%.o: $(_MODULE_PATH)/%.c | $(_OUTPUT_TREE)
#$(COMPILE.c) -o '$#' '$<'
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_LIBEXT): $($(_MODULE_NAME)_OBJS)
#if [ "$(LIBMERGE)" = "F" ]; \
then \
$(AR) r '$#' $^; \
ranlib '$#'; \
else \
libtool -static -o '$#' $^; \
fi
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_EXEEXT): $($(_MODULE_NAME)_OBJS)
$(LINK.c) $^ -o '$#'
.PHONY: output-tree $(_OUTPUT_TREE)
output-tree: $(_OUTPUT_TREE)
$(_OUTPUT_TREE):
mkdir -p $($(_MODULE_NAME)_OUTPUT)
$(_MODULE_NAME)_DEFINED := T
endif
endif
I added a prerequisite order to the atomic target
$($(_MODULE_NAME)_OUTPUT)/%.o: $(_MODULE_PATH)/%.c | $(_OUTPUT_TREE)
Here is the rule:
.PHONY: output-tree $(_OUTPUT_TREE)
output-tree: $(_OUTPUT_TREE)
$(_OUTPUT_TREE):
mkdir -p $($(_MODULE_NAME)_OUTPUT)
I'll see if I need more adjustments but it seems to be the right way !
I have a template file, and the configuration script transforms it into the final Makefile. What shoud be the extension of the template?
Example template:
EXEC = $var1
PATH = $var2
CC = $var3
STRIP = $var4
MKDIR = $var5
COPY = $var6
.PHONY: all
all: $(EXEC)
$(EXEC): source.c
$(CC) $< -o $#
$(STRIP) $#
$(MKDIR) $(PATH)
$(COPY) $# $(PATH)/
The variables are replaced by the configuration script.
My recipe $(HDAIMG) is always been processed, even when already there is a $(HDAIMG) file in the folder. What am I doing wrong?
HDAIMG := $(TESTDIR)/$(PROJECT)-hda.img
HDAIMG value, actually, is test/project-hda.img
PHONY: $(PROJECT)
all: $(PROJECT) $(HDAIMG)
$(PROJECT): check-env
$(call v_exec, 1, $(MAKE) -C $(SRCDIR) $#)
$(HDAIMG): $(PROJECT) check-env
$(call print_white_init, HDAIMG)
$(call print, Creating $#)
$(call v_exec, 2, dd if=/dev/zero of=$# count=0 bs=1 seek=$(HDAIMGSIZE) &> /dev/null)
$(call print, Partitioning $#)
$(call v_exec, 2, parted --script $# mklabel msdos mkpart primary ext4 1 100%)
$(call print, Creating $# device maps)
$(call v_exec, 2, sudo kpartx -a $# -s)
$(call v_exec, 2, sudo mkfs.ext4 /dev/mapper/loop0p1 -q)
$(call v_exec, 2, sudo mount /dev/mapper/loop0p1 $(TESTDIR)/mnt)
$(call v_exec, 2, sudo umount $(TESTDIR)/mnt)
$(call v_exec, 2, sudo kpartx -d $#)
$(call print_white_done, HDAIMG)
check-env:
ifneq ($(ERROR),)
$(call print_error, $(ERROR))
exit 1
endif
That called functions are used to print with color or to execute with choosed verbose; there are in my Makeconfig.mk already included. Some:
v_exec = $(V$(strip $(1)))$(strip $(2))
print = #echo -e '$(LEAD_SUB_STR) $(strip $(1))'
print_white_init= #echo -e '$(subst PATTERN,$(strip $(1)),$(WHITE_INIT)) $(strip $(2))'
print_white_done= #echo -e '$(subst PATTERN,$(strip $(1)),$(WHITE_DONE)) $(strip $(2))'
$(HDAIMG) has check-env as a prerequisite, and Make always thinks that check-env must be rebuilt, because check-env is not actually a file that exists. Therefore Make decides that $(HDAIMG) must be rebuilt.
It would make more sense to perform the check as the first command in the rule, rather than as a prerequisite.
I want to do something like:
for i in *
do
if test -d $i
then
cd $i; make clean; make; cd -;
fi;
done
And this works fine, but I want "break" the for-loop in case of a broken build.
Is there a way to do this? Maybe some kind of if-statement, that can check for success of make?
You can use Make itself to achieve what you're looking for:
SUBDIRS := $(wildcard */.)
.PHONY : all $(SUBDIRS)
all : $(SUBDIRS)
$(SUBDIRS) :
$(MAKE) -C $# clean all
Make will break execution in case when any of your target fails.
UPD.
To support arbitrary targets:
SUBDIRS := $(wildcard */.) # e.g. "foo/. bar/."
TARGETS := all clean # whatever else, but must not contain '/'
# foo/.all bar/.all foo/.clean bar/.clean
SUBDIRS_TARGETS := \
$(foreach t,$(TARGETS),$(addsuffix $t,$(SUBDIRS)))
.PHONY : $(TARGETS) $(SUBDIRS_TARGETS)
# static pattern rule, expands into:
# all clean : % : foo/.% bar/.%
$(TARGETS) : % : $(addsuffix %,$(SUBDIRS))
#echo 'Done "$*" target'
# here, for foo/.all:
# $(#D) is foo
# $(#F) is .all, with leading period
# $(#F:.%=%) is just all
$(SUBDIRS_TARGETS) :
$(MAKE) -C $(#D) $(#F:.%=%)
You can check whether the make has exited successfully by examining its exit code via the $? variable, and then have a break statement:
...
make
if [ $? -ne 0 ]; then
break
fi