From my understanding of how virtual address translation happens (assuming a 32 bit virtual address space, as in the x86 architecture):
bits 31:22 of the virtual address indicate the proper Page Directory Entry (i.e. aligned physical address of the Page Table) to access
similarly, bits 21:12 of the virtual address indicate the proper Page Table Entry (i.e. aligned physical address of the Page itself) to access
lastly, bits 11:0 indicate the proper offset into the Page, and are merely appended onto the end of the final physical address to access
As for the physical address
bits 31:12 are the physical base address (aligned) of the Page (found from the PTE)
bits 11:0 are the same as they are in the virtual address
Visually, this is what happens
I know that a Page is a chunk of virtual memory. But conceptually, I have a hard time visualizing what is actually "inside" of a Page. Ie, if I were to index into a "Page entry" (if such a thing even makes sense), what would I get in return?
This post
seems to refer this value as a "desired byte." What exactly is the "desired byte"? Am I overthinking the functionality of Pages?
From reading your question, it sounds like your misunderstanding is because you do not understand the format of a page table entry.
The memory management unit (MMU) of the CPU divides the physical memory into PAGE FRAMES of some fixed size (typically 512K to 1MB).
The operating system manages PAGES of memory.A page must have the same size as the page frame. User mode processes only see pages; not page frames.
The operating system maintains sets of PAGE TABLES that provide the mapping between the pages and page frames.
In a logical memory system, the bits within an address consists of two bit fields. One bit field identifies the page and the other specifies the byte offset into the page.
When a process accesses an address, the MMU divides it into the two bit field. It then uses the page identifier to look up the what page frame the page is mapped to in the page tables.
. Ie, if I were to index into a "Page entry" (if such a thing even makes sense), what would I get in return?
The page entry (or entry in the page table) specifies the number of the physical page frame.
[This is the part it sounds like you are missing.]
In your example, you discuss a multi-level page table, but for simplicity, let's assume there is no page directory, and just a page table.
In a 32-bit system, the page entry will typically be 32-bit and 64-bits on a 64-bit system. The format of the page entry varies among system but it will likely have bit fields that define:
The index of the page frame mapped to.
Bits indicating if the entry is valid.
A bit the indicates if the corresponding page has been written to.
Bits the specify the protection for the page.
In your example you have omitted the format of the page table entry.
So once you have the entry, the next step is to get the page frame from it.
In your example, this is 4096 bytes of data.
The MMU could either just use the page frame index to identify the page. Or it could multiply that value by the page size to get the byte that starts the page.
To get the specific byte within the 4096, the MMU uses the offset (bits 0:11 in your example)
The MMU does all this behind the scenes so the process never sees it. One of the chief jobs of the operating system is to maintain the page tables and the entries within them.
You can think of each page as a 4096 byte "array". (On x86 with 4k pages). It's not an "array" in the high-level-language sense of the word (unless you happen to have a page-aligned array of bytes in your program), but it is a linear collection of bytes that you can index with an offset.
A one-byte load from any specific address has an offset within a specific page, which determines which of those 4096 bytes should be loaded. The low 12 bits of the address determine this offset. (i.e. the "page offset").
Note that 2^12 = 4096, that's why it's the low 12 bits that represent the offset within the page in an address.
Further reading: What Every Programmer Should Know About Memory?
Related
While studying virtual memory concepts, I understood that a virtual address (generated by a processor to access memory location) contains page number and page offset. we use a page table to get the physical address (frame number essentially) corresponding to this page number.
Now, if these addresses (physical/virtual) operate in terms of pages/frames, how does the processor access a cache which operates in terms of blocks/lines?
Also, if the virtual address consists of only page number and page offset, where does the tag bits come from which is used to check if the cache set (specified by index/set bits) contains the required data or not?
I figured out the answer to this question.
Same address can be used/interpreted for accessing two different addressing schemes. (Thanks #PeterCordes for pointing this out)
Scheme 1 (To access the TLB): PageNumber + PageOffset
Scheme 2 (To access the cache): Tag + Set/Index + Offset
Usually in VIPT caches, the page number comes from higher-order TAG bits, and the page offset comes from lower-order TAG bits along with SET and OFFSET bits. To prevent aliasing (multiple virtual addresses mapping to same physical address), it is important that SET/INDEX bits come fully from page offset. This restriction limits the size of the cache.
Im having trouble understanding the process of finding the virtual page offset, the value of the physical page offset, and the virtual page number
Ive tried looking at various places but I cannot find any examples or formulas for finding the following parameters. Below is an example of a problem, but I have left out the virtual address from the actual problem.
Given a virtual memory system with the following specification:
The memory is byte addressable.
Each memory access is to 1-byte word.
Each virtual address is 16-bit wide.
Each physical address is 12-bit wide.
The page size is 32 bytes (25)
The TLB is 4-way set associative with 16 total entries.
The L1 data-cache is physically addressed and direct mapped, with a 4 byte line size and 16 total sets.
If the CPU issues the following virtual address: (some hex number)
What is the virtual page offset?
What is the value of the physical page offset?
What is the value of the TLB tag?
What is the value of the TLB index?
What is the value of the virtual page number?
(Answers in binary)
After turning the hex number to binary, I am lost. How can I find the virtual page offset? Whats the difference between the virtual page offset and the physical page, and how do I find the value of the physical page?
I think the TLB tag is the remaining digits after the VPO and PPO, but I would need to know how to get the VPO and the PPO first. I am unsure what the TLB index is. The VPN is a combination of some of these answers but I am not sure which.
What happens if the set associative is changed to a 2 way TLB? does that change the way I find these values?
Finally, If I were given a 2-way set associative TLB and a page table with the same information above, how can I determine if there is a page fault or not? From what I understand, if there is a TLB hit there is no page fault, but if not, how can I determine this? He also talks about a physical address, what is the process of finding this?
What is the virtual page offset?
What is the value of the physical page offset?
VPO are addresses of a byte within a page. Concerning physical pages, they are generally called frames, but the offset definition is identical.
VPO = VAdr % PageSize
What is the value of the TLB tag?
What is the value of the TLB index?
TLB index maps a VAdr to a TLB set.
Number-of-sets = number-of-TLB-entries / number-of-ways
and ìndex-size =log_2(number-of-sets)
TLB tag is the remaining MS bits in virtual address
What is the value of the virtual page number?
Virtual-page-number = virtual-adresse / page-size
If address is in binary abdefghijklmnopq its interpretation as (TLBTag,TLBidx,VPO) is (abdefghij,kl,mnopq) and virtual page address is abdefghijkl.
What happens if the set associative is changed to a 2 way TLB? does that change the way I find these values?
If the number of entries is unchanged, this divides the number of sets by 2 and adds one bit to TLBIdx (and removes one from TLBTag).
Finally, If I were given a 2-way set associative TLB and a page table with the same information above, how can I determine if there is a page fault or not? From what I understand, if there is a TLB hit there is no page fault, but if not, how can I determine this?
If there is a TLB hit, there is no page fault. If there is a TLB miss, page address has to be generated by looking at process page tables. These tables indicates correspondence between virtual and logical page addresses and if a page is in memory or swapped to disk. If the page is swapped to disk, this is a page fault. This generates an exception and the OS has to write the page back to memory.
He also talks about a physical address, what is the process of finding this?
For simple situations like yours, it can just be a table lookup. A page address is 11 bits wide and a 2048 entry table indicates the address of the corresponding physical frame. In real systems, this is more complex and generally involve several cascading tables.
What is the virtual page offset?
Address MOD Page Size
What is the value of the physical page offset?
Address / Page Size
What is the value of the TLB tag?
Unknown from what you have given.
What is the value of the TLB index?
Unknown from what you have given.
What is the value of the virtual page number? (Answers in binary)
Address / Page Size
As far as my understanding goes, the CPU always generates a virtual address that is made-up of 2 parts- the page number and the page offset. The page number is used for indexing the page table (the corresponding mapping gives the starting address of the frame in the RAM). Now, please consider the following questions. Consider that the word size of the machine is 4 bytes, and the page size is equal to the frame size = 4096 bytes.
Supposing that the page number is 4 and the offset is 3. Then Page 4 in the logical memory maps to frame 8 in the virtual memory. This means that the starting address of the frame is 8.
Now, each frame will contain 4096/4= 1024 words. Does the offset imply for a word inside the frame, since the machine will always fetch a word at a time? What I mean is that does it mean the 3rd word in frame 8?
Is the particular word given to the CPU, or the entire frame? If former, then why does everyone talk about transfer in terms of frames and pages rather than words?
Suppose a page fault occurs. What this means is that the particular page in not in memory. Does it mean that the physical address mapped contains some other page? Does the mapping even exist in such a case when the invalid bit is 1.
Can someone clear-up things for me? One moment I seem to get it, and the very next, I get into a maze.
The key point of paging is that it deals with "chunks" of memory.
It is a map, a function, that translates virtual addresses into physical addresses but not on an address-by-address base. Rather, a "chunk" of continuous virtual addresses is translated together into another continuous "chunk" of, now physical, addresses.
You can think of it as a "translation" or "shuffle" of "chunks" of memory.
The correct term for "chunk" is page.
If try to do a sample mapping you can see that each page contains a set of addresses that all have a peculiarity: their lower bits don't change when passing from virtual to physical. The upper bits instead are arbitrary.
This dichotomy of the address value defines the Offset and Page/Frame number.
The offset is the part of the address value that don't undergo any translation.
In a page of 4KiB there are 4096 addresses, each one with its offset, so the offset has size log2(4096) = log2(212) = 12 * log2(2) = 12 bits.
In short the page size determines the offset size.
It is necessary to break the memory into pages and not words or byte, or in another view it is necessary to group the addresses to translate into pages.
Without pages, the metadata used for the translation, in jargon the page tables of various level, would occupy more memory that the one that under translation!
Offsets are relative to their page/frame thanks to the way their are defined: the offset 1024 (in hex 400h) in the frame 8 means the address 8000h + 400h = 8400h; if the page is mapped to the frame 12 the offset 1024 is still 1024 bytes after the beginning of the frame, 0c000h + 400h = 0c400h.
Being an address, an offset usually denotes a byte, event in architecture where bytes are not addressable. However this is not a standard convention, to know if an offset denotes a word or a byte (e.g. if offset 10 of frame 0 is the byte 40 or the byte 10) check the architecture manual. The first sections are usually dedicated to establishing a terminology to use throughout the book.
Paging happens before the CPU accesses the memory, you can think of it as an high level process. The unit that accesses the memory/bus is mostly unaware of it, as such the CPU read the data that the instruction is telling it to read (a word, a byte, and so on).
People talk about moving a page because a page is the smallest unit that can be characterized.
You can mark a page as non present, but not a word. You can make a page read-only but not a word.
If you need to map, say 16 bytes, you still need to map a whole page since 16 bytes are not characterizable. So we might as well read a whole page.
When a page-fault occurs it means that the page accessed is, at any level in the page-tables, non present.
This may mean a wide range of things, from the fact that the Present bit has been simply toggled (with the page still there), to the fact that the page has been saved to disk and zero-ed in memory.
Since the mapping function is total, meaning that every value is a valid value, the CPU need a way to know when a value is not valid.
The Present bit does this: tell the CPU that a translation must not be performed and that an exception must be raised instead.
The OS use this exception to be notified of when a page is needed, it doesn't need to reassign the mapping to another page or zero the memory.
When people say that a page is removed they mean that it is removed from the mapping, all modern OSes also zero-d the page to prevent leaking of information to other processes though.
So if a physical frame is not mapped it doesn't mean that another page in another process is mapping it, it simply mean that that range of addresses cannot be accessed.
As said above there are a lot of reasons for an OS to do this, including protection.
You have things a bit backwards. The operating system defines a logical address space for each process. The logic address space is divided into units of memory called PAGES.
The operating system logically maps the pages of the address to either physical page frames or secondary storage If the operating system maps pages to secondary storage then is using virtual memory.
In ye olde days all systems that did logical memory translation always did virtual memory mappings to secondary storage. That is why the terms virtual memory translation and logical memory translation are often conflated. These days it is becoming increasingly common to have logical translation without virtual memory.
All address accesses through a process are to logical addresses. The processor translates the logical address to page frames. If logical page exists but is mapped to secondary storage, accessing that page triggers a page fault. The operating system must handle the fault, remap the logical/virtual page to a physical page frame; load the data from secondary storage to the page frame; and restart the instructions.
Supposing that the page number is 4 and the offset is 3. Then Page 4 in the logical memory maps to frame 8 in the virtual memory. This means that the starting address of the frame is 8.
This make no sense. A logical page is virtual when it is mapped to secondary storage. If the page number is 4 the 4th logical page can:
a) have no mapping at all (access violation)
b) map to a physical page frame
c) map to a secondary storage (virtual memory)
Now, each frame will contain 4096/4= 1024 words. Does the offset imply for a word inside the frame, since the machine will always fetch a word at a time? What I mean is that does it mean the 3rd word in frame 8?
In nearly all (if not all) current processors there are no memory words; only bytes. The system bus fetches memory and the "word size" of the bus can be (and often is) different from the "word size" of the processor.
Is the particular word given to the CPU, or the entire frame? If former, then why does everyone talk about transfer in terms of frames and pages rather than words?
The process sees transfers in sizes related to the instruction being executed. The operand size can be larger or smaller than the machine word. The bus transfers data to memory and that size is frequently different from the word size of the machine.
Suppose a page fault occurs. What this means is that the particular page in not in memory. Does it mean that the physical address mapped contains some other page? Does the mapping even exist in such a case when the invalid bit is 1.
I gave the three possibilities for logical page mappings above. How those are indicated are system specific. Some systems use 2 bits to indicate a, b, or c. Others use a single bit to indicate (b) and require the operating system to determine whether it's (a) or (c).
Whether or not a page fault is triggered depended upon the state of the page table.
Generally a page fault means that the page frame is not in memory. However, it is often possible for the physical page frame to be in memory but not mapped in the page table (a soft page fault). (This occurs when the operating system has unmapped page frames to free some up but has not reallocated them.) In this case, the operating system simply needs to update the page table to point to the page frame and restart the instruction (no need to load from secondary storage).
In the answer(in the book), I am not getting the following-
"The starting address of an n-bit page frame is a multiple of 2^n. Thus, the bit pattern of the frame's starting address consists of the frame number followed by n 0's."
Please explain.
You need another book.
The starting address of an n-bit page frame is a multiple of 2^n. Thus, the bit pattern of the frame's starting address consists of the frame number followed by n 0's."
That's nonsense or at least partial nonsense. It presumes that page frames are addressed, rather than indexed.
In a real mode, memory is addressed, but there are no page frames. When logical memory translation is used, page frames are indexed on every system I have seen.
If page frames were addressed as suggested in your book,
1) A system could not have more physical memory than can be addressed using the CPU's word size; and
2) The page tables would be unnecessarily large because they would have to account for both the full address of the page frame AND any overhead bits.
Normally, page tables use the spare bits from the page size for page management overhead.
IF the first byte in a page frame were to be accessed in real mode, then such a byte would address would be a multiple of the page size (which is always a power of 2). Thus, the lower bits in the address would be some string of zeros. But in virtual/logical translation page frames do not have addresses.
I do not understand why these operating systems books insist on confusing the subject.
Lets consider that size of page is equal to 1 KB. One entry in table
takes 2B. Table of pages takes not more than one page (so <= 1KB).
Can we conclude that size of operational memory is <= 512 KB ?
A correct answer is No, however I can't understand it. For me, answer is yes - look at my reasoning at show me where I am wrong, please.
Table contains <=1024B/2B=512=2^9 entries in table of pages. Size of page is 1024B=2^10B, so offset takes not more than <=10 bits. Number of page takes <=9 bits - because we have 512=2^9 entries. Hence, 9+10=19. Therefore <=2^19 bits make it possible to address <= 2^19 B=2^9KB=512KB.
Where am I wrong?
A page table entry is 2B, so a table entry can point to one of 2^16 physical pages. That's 2*16 kiB (because pages are 1kB). So a kernel can make use of up to 65536 kiB (64MiB) of physical memory.
This assumes that the entire page table entry (PTE) is a physical page number. That can work if the position of a PTE within the page table associates it with a virtual address. i.e. 9 bits of a virtual address are used as an index into the PT, to select a PTE.
We can't assume that the machine does work this way, but similarly we can't assume that it doesn't, until we have more information.
Given just the info in the question, we can conclude:
Usable physical memory can be anything up to 65536kiB.
Up to 512 virtual pages can be mapped at once (512kiB).
Not much else! Many possibilities are open.
A more likely design would have a valid/invalid bit in each PTE.
If a PTE's contents (rather than its location) indicate which virtual page it maps, it would be possible to map a large virtual address space onto very few physical pages. This address space would necessarily be sparsely mapped, but the kernel could give a process the illusion of having a lot of active mappings by keeping a separate table of what the mappings should be.
So on a page fault, the kernel checks to see if the page should have been mapped. If so, it puts the mapping in the PTE and resumes the process. (This kind of thing happens in real OSes, and it's called a minor page fault.)
In this design, the kernel's use of the page table to hold a subset of the real mappings would be analogous to a software-managed TLB. (Of course, this architecture could have a non-coherent TLB that requires invalidation after every PTE modification, so this would probably perform horribly).