There is an AES instruction or a DRNG instruction of the Intel CPU.
I would like to know if there is such an instruction on the AMD CPU or similar command.
Or is there a web site where i can get information about this?
Related
If we have a dual-core ARM CPU, does that mean we also have all COprocessors as "dual-cored"?
I mean, do we have two sets of cp14 or cp15 registers in this case?
Thank you!
I believe each core would have the same debug hw registers IF the maker of the SOC device compiled that silicon IP into each core (which is likely). You'll have to interrogate each core to see if it's supported. Then you'd have to execute the instructions accessing CP14 etc from the core in question (to access its CP14)
I am writing a debugger that should trace a guest OS execution in a virtual machine. Intel VMX Monitor Trap Flag field enables us to single step a guest OS instruction.
But I am working with AMD processor and I don't find in the documentation any equivalent for this. Does someone know if there is any AMD SVM equivalent for the Intel VTX Monitor Trap Flag ?
I am using laptop with below configuration.
Processor: Intel(R) Core(TM)i5-4300U CPU #1.90GHz 2.49GHz
RAM: 8GB
System Type:64-bit OS, x64-based processor
Windows Edition:Windows 8.2 Enterprise
When I was reading about CPU architectures, i wanted to know what CPU architecture followed in my computer?
Your processor is a modified Harvard Architecture. The reason why it is a modified Harvard Architecture is that it has split instruction and data L1 caches. Except for this, it is a von-Neumann architecture - instructions and data can both be present in the other cache levels and main memory.
The distinction between the two is relevant only when instructions are treated as data, such as in self-modifying code or Just In Time compilers.
I am currently trying to access the registers of the ARM9 core on the Zynq Z702 SoC using the XIlinx's XMD tool provided as part of the SDK. When I try to read a part of memory, I am getting an MMU related error. Do i need some specialized hardware to read and write to these registers when running an OS on the processor. Please help.
P.S. : I am running Linux 3.x.x kernel on the processor and the memory region I am trying to access are memory mapped regions and are not occupied by any kernel or user-space code.
I have a Freescale's i.MX515EVK, an ARM Cortex-A8/Ubuntu platform with me, unfortunately the Linux kernel on the board is not supporting some of the well known profilers such as Oprofiler or Zoom Profiler(Zoom supports ARM processors, but it internally, uses Oprofiler driver) which give very detailed reports about the cache utilization.
Cortex-A8 has 32KB Instruction and Data caches and a 256KB L2 Cache. Currently when my image processing algorithm is running, I'm totally blind about their usage.
Are there any other methods, other than using profilers to find out cache hits and misses?
Install Valgrind (it supports ARM nowdays) and use the cachegrind tool to check cache utilization. If you are running Ubuntu on the device, it should be as simple as sudo apt-get install valgrind. Valgrind can also help you simulate what would happen with different cache sizes.