Passing variable upward from makefile targets - makefile

Question

I have several targets in the Makefile. Each target add some values to the makefile variable. For example, CFLAGS.
CFLAGS := 1
a: CFLAGS += 2
b: CFLAGS += 3
I need to write target "с" which will "see" values assigned in "a" and "b". And which, may be, add some more values.
I tried to do it like this:
c: CFLAGS += 4
c: a b
echo ${CFLAGS}
Here I planned to see CFLAGS equal to "1 2 3 4" or "1 4 2 3"
But in fact CGLAGS will be equal to:
a: 1 4 2
b: 1 4 3
c: 1 4
Sample Makefile:
CFLAGS := 1
.PHONY: all a b c
all: c
a: CFLAGS += 2
a:
echo TargetA ${CFLAGS}
b: CFLAGS += 3
b:
echo TargetB ${CFLAGS}
c: CFLAGS += 4
c: a b
echo TargetC ${CFLAGS}
Any way to do this?
PS. Some reasoning for ones who want to.
I have some programs that needs libA. Target "a" that have inclides/libs for libA and is used for these programs.
I have some programs that needs libB.
And I have some programs that needs all: libA, libB and libC.
I want to "reuse" targets "a" and "b" to avoid making assignment duplication.

Answer 1

As mentioned in the other comment, you have the prerequisite relationship backwards to get the behavior you want.
Rather than writing a lot of call and eval functions, I would prefer to use computed variable names here. You can do something like this:
CFLAGS = 1
CFLAGS_a = 2
CFLAGS_b = 3
CFLAGS_c = 4
all: c
c: a b
a b c:
#echo '$(CFLAGS) $(CFLAGS_$#) $(foreach P,$<,$(CFLAGS_$P))'
to print the default CFLAGS, then the CFLAGS for the target, then the CFLAGS for each prerequisite. Of course you'll have to modify this for your specific purposes.
For more information on different types of "metaprogramming" in GNU make, you can read this set of blog posts. Start with the first one (which is at the end of that list, unfortunately).

Answer 2

Problem
From GNU Make's manual section on target-specific variables:
when you define a target-specific variable that variable value is also in effect for all prerequisites of this target, and all their prerequisites, etc.
In your makefile, a and b are prerequisites of c, so setting CFLAGS as a c's target-specific variable does have effect also in a and b. Not the other way around, i.e.: setting CFLAGS as an a or b's target-specific variable has no effect in c at all, since it is not a prerequisite of any of them.
Possible alternative
If your motivation for achieving such a thing, is that a target may need an arbitrary combination of any of libA, libB or libC. Then, I would suggest you to define the variables libA, libB, libC, libAB, libAC, libBC and libABC that represent the corresponding library combinations and then include one of those variables to the corresponding target as prerequisite.
The following makefile may serve as a starting point and clarifies what I want to express as well:
.PHONY: all
libsCommon := 1
libsA := $(libsCommon) 2
libsB := $(libsCommon) 3
libsC := $(libsCommon) 4
# $(call include-to,varSrc,varDst)
# for avoiding repetition of libraries
define include-to
$(eval $2 += $(filter-out $($2),$($1)))
endef
# libsAB
$(call include-to,libsA,libsAB)
$(call include-to,libsB,libsAB)
# libsAC
$(call include-to,libsA,libsAC)
$(call include-to,libsC,libsAC)
# libsBC
$(call include-to,libsB,libsBC)
$(call include-to,libsC,libsBC)
# libsABC (all)
$(call include-to,libsA,libsABC)
$(call include-to,libsB,libsABC)
$(call include-to,libsC,libsAll)
all:
#echo "libsA: $(libsA)"
#echo "libsB: $(libsB)"
#echo "libsC: $(libsC)"
#echo
#echo "libsAB: $(libsAB)"
#echo "libsAC: $(libsAC)"
#echo "libsBC: $(libsBC)"
#echo
#echo "libsABC: $(libsABC)"
Running make with this makefile produces:
libsA: 1 2
libsB: 1 3
libsC: 1 4
libsAB: 1 2 3
libsAC: 1 2 4
libsBC: 1 3 4
libsABC: 1 2 3 4
This approach, however, won't scale well when you have many libraries or different possible combinations of them.
In any case, I would strongly recommend that if target a does need libA, then libA should be made a prerequisite of a.