ARM L2 Cache access count differs when stepping though code - performance

Question

I am using OpenOCD to run a program on an embedded board with an ARM Cortex-A9 (a Zynq-7010; I'm using a single core running a baremetal program).
I would like to be able to figure out if each memory access results in a cache hit or a cache miss. The L2 Cache Controller, an L2C-310, provides two counters which I have configured to count Data Read Hits and Data Read Lookups (which result in either a hit or a miss).
The problem is that I get different results when I execute the program without stopping compared to when I execute the program and step through each line. My specific question is: Why is there a difference and is there a way that I can make the output uniform? More generally: Is it possible to determine if a specific line of assembly resulted in a cache hit?
I am controlling OpenOCD using a python script. I am disabling the L1 caches (not shown), turning off pre-fetching, and (I think) turning off the pre-load engine. Here is the code I am running when executing the program without stopping:
# A this point, the program has be loaded, and allowed to execute up until the start of the code section I am measuring
telnet = Telnet('127.0.0.1', 4444, 300)
end_addr = 0x100930 # End of code section I am measuing
### 1) Pre-Fetch / Pre-Load stuff ####################
# Turning off the pre-fetch option. Should read, change mask, then write
print('\tSetting pre-fetch option to off\n')
telnet.write('arm mcr 15 0 1 0 1\n')
response = telnet.read_until('arm mcr 15 0 1 0 1\r\n')
response = telnet.read_until('\r>')
print('Response: %s' % (response))
actlr = int(response[:-2])
print('actlr: %d' % (actlr))
actlr = actlr & (~(1 << 2)) # Disable L1 Pre-fetch
actlr = actlr & (~(1)) # Disable TLB / Cache maintenance fwd
print('actlr: %d' % (actlr))
# write to telnet
telnet.write('arm mrc 15 0 1 0 1 ' + str(actlr) + '\n')
telnet.write('arm mcr 15 0 1 0 1\n')
response = telnet.read_until('arm mcr 15 0 1 0 1\r\n')
response = telnet.read_until('\r>')
print('Response: %s' % (response))
print('attempting to pause pre-load engine:')
telnet.write('arm mrc 15 0 11 3 0 0\n')
######################################################
### 2) Enable L2CC counters ##########################
telnet.write('mww 0xF8F02200 0x1\n') # enable counting
# confirm enabled
telnet.write('mdw 0xF8F02200\n')
response = telnet.read_until('mdw 0xF8F02200\r\n')
response = telnet.read_until('\r>')
print('Response should be 1: %s' % (response))
# Counter 0: 0011 to set source to Data Lookup, 01 for increment
telnet.write('mww 0xF8F02208 0xD\n')
# confirm counter 0 settings
telnet.write('mdw 0xF8F02208\n')
response = telnet.read_until('mdw 0xF8F02208\r\n')
response = telnet.read_until('\r>')
print('Response should be 0xD: %s' % (response))
# Counter 1: 0010 to set source to Data Read Hit, 01 for increment
telnet.write('mww 0xF8F02204 0x9\n')
# confirm counter 1 settings
telnet.write('mdw 0xF8F02204\n')
response = telnet.read_until('mdw 0xF8F02204\r\n')
response = telnet.read_until('\r>')
print('Response should be 0x9: %s' % (response))
######################################################
### 3) Different from step mode ######################
print("Setting end tag to 0x%x" % (end_addr))
# Set breakpoint to end of section
telnet.write('bp ' + str(end_addr) + ' 1 hw\n')
telnet.write('resume\n')
response = telnet.read_until('resume\r\n', 1)
response = telnet.read_until('>', 1)
# Allow program to execute
sleep(10)
######################################################
### 4) Check L2CC counters ###########################
# Counter 0: number of data lookups
telnet.write('mdw 0xF8F02210\n')
response = telnet.read_until('mdw 0xF8F02210\r\n')
response = telnet.read_until('\r>')
print('Data Lookups: %s' % (response))
# Counter 1: check number of data read hits
telnet.write('mdw 0xF8F0220C\n')
response = telnet.read_until('mdw 0xF8F0220C\r\n')
response = telnet.read_until('\r>')
print('Data Read Hits: %s' % (response))
system('exit')
The results of which are:
Data Lookups: 0xf8f02210: 00000660
Data Read Hits: 0xf8f0220c: 000004c2
When I run the code by stepping through each instruction, the number of data lookups ends up being the same as the number of read hits... so where did those cache misses go?
Here is the changed code (chunk number 3):
### 3) Different from continuous mode ##############
print("Setting end tag to 0x%x" % (end_addr))
cur_addr = step()
# Run until the end tag
while cur_addr != end_addr:
cur_addr = step()
And the step() function:
# Commands OpenOCD to step the processor forward
# Returns the new pc address
# Sorry for the messy error checking!
def step():
telnet.write('step\n')
response = telnet.read_until('step\r\n', 1)
# print('Step: %s ****' % (response))
# Skip line of output
response = telnet.read_until('\n', 1)
# print('Step: %s ****' % (response))
# 2nd line has the pc, 4th column
response = telnet.read_until('\n', 1)
# print('Step: %s ****' % (response))
try:
cur_addr = int(response.strip().split()[3], 16)
except (ValueError, IndexError) as e:
print("Error step() on line: ", response)
print("\tException: ", e)
countdown = 20
error = True
while (countdown > 0):
countdown = countdown - 1
response = telnet.read_until('\n', 1)
#print("Retry on line: ", response)
if ('cpsr' in response): # TODO: Maybe just read until this anyways?
print("Found a match.\n")
cur_addr = int(response.strip().split()[3], 16)
countdown = 0
error = False
if error:
# try sending again?
telnet.write('step\n')
response = telnet.read_until('step\r\n', 1)
print('Step: %s ****' % (response))
# Skip line of output
response = telnet.read_until('\n', 1)
print('Step: %s ****' % (response))
# 2nd line has the pc, 4th column
response = telnet.read_until('\n', 1)
print("Failed to recover from error? Retried:", response)
cur_addr = int(response.strip().split()[3], 16) # This line should fail
response = telnet.read_until('>', 1) # skip remaining
return cur_addr
And the output:
Data Lookups: 0xf8f02210: 000004c2
Data Read Hits: 0xf8f0220c: 000004c2
Thank you for your time, and I appreciate any help.