executing mux or decode in register - vhdl

Question

Mux alone works , Decoder alone works
Now I want to choose which one to use based on my write_ena in code.
I tried making process and if-else but didn't work and errors in it
My code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:49:06 04/01/2018
-- Design Name:
-- Module Name: RegisterFile - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_LOGIC_arith.all;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
USE WORK.mux_pkg.ALL;
USE WORK.decoder_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RegisterFile is
Port ( read_sel1 : in STD_LOGIC_VECTOR (4 downto 0);
read_sel2 : in STD_LOGIC_VECTOR (4 downto 0);
write_sel : in STD_LOGIC_VECTOR (4 downto 0);
write_ena : in STD_LOGIC;
clk : in STD_LOGIC;
write_data : in STD_LOGIC_VECTOR (31 downto 0);
data1 : out STD_LOGIC_VECTOR (31 downto 0);
data2 : out STD_LOGIC_VECTOR (31 downto 0)
);
end RegisterFile;
architecture Behavioral of RegisterFile is
begin
process (write_ena)
variable r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30,r31: STD_LOGIC_VECTOR (31 downto 0);
variable temp : STD_LOGIC_VECTOR (31 downto 0);
begin
if (write_ena = '1') then
D1: decoder PORT MAP (write_sel,temp);
elsif (write_ena = '0') then
M1: mux PORT MAP (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30,r31,read_sel1,data1);
M2: mux PORT MAP (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30,r31,read_sel2,data2);
end if;
end process;
end Behavioral;
I have package for mux and package for decoder
Errors i get:
ERROR:HDLCompiler:806 -Line 66: Syntax error near "PORT"
ERROR:HDLCompiler:806 -Line 70: Syntax error near "PORT"
ERROR:HDLCompiler:806 -Line 71: Syntax error near ";"
and so on till the end of my process
QUESTION:
I understand that I cannot initiate port inside process so my question is:
How to choose just one to work (either mux or decoder) inside my architecture