I need your help. I have a VHDL with nested condition and I would like to redraw it into a schematic. I think I should use one 2bit mux and 4bit mux. Is there anyone who can help me please? I tried google it but I didn't find anything that can help me.
process (a,b,c,d) begin
y <= '0';
z <= b;
if d='1' then
y <= b;
if a = '0' then
y <= c;
end if;
z <= '1';
else
y <= '1';
z <= d;
end if;
end process;
a,b,c,d are std_logic in
z, y are std_logic out
This a code for a 4-bit mux you can easily modify to make 2 bit
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux_4_1 IS
PORT (
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
b : OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE behavioural OF mux_4_1 IS
BEGIN
PROCESS (a, s)
BEGIN
IF s = "00" THEN
b <= a(0);
ELSIF s = "01" THEN
b <= a(1);
ELSIF s = "10" THEN
b <= a(2);
ELSE
b <= a(3);
END IF;
END PROCESS;
END ARCHITECTURE;
Related
I wrote this code to understand process in vhdl but strangely I saw the simulation that doesn't work properly
my code :
entity test is
port(
i1 : in std_logic;
i2 : in std_logic;
r : out std_logic
);
end test;
architecture Behavioral of test is
signal g : std_logic;
begin
process(i1)
begin
if i1 = '1' then
g <= '1';
else
g <= '0';
end if;
end process;
process(i2)
begin
if i2 = '1' and g = '0' then
r <= '1';
else
r <= '0';
end if;
end process;
end Behavioral;
and this is my result :
enter image description here
when i process i1 so g should be 1 in the first period so r should be 0 but r is 1 after i2 is 1
Your are using g in the second process but it is not in the process sensitivity list.
process(i2,g)
begin
if i2 = '1' and g = '0' then
...
i am trying to do an algorithm that verify prime numbers. To do this i have to make a circuit using RTL Design method, i am using the algorithm below to get the prime number:
int prime (int x) {
int i, div;
div = 0;
for (i = 1; i <= x; i++){
if (mod(x, i) == 0)
div++;
}
if (div == 2)
return 1; // PRIME
else
return 0; // NPRIME
}
To implement this solution I created two blocks: Datapath and Control like the image below:
My datapath has 4 intern blocks:
for_reg --> register that control the loop for of the prime algorithm (have a flag to indicate when the loop ends)
buffer --> Makes the output equal the input
modulo --> Get the mod of the div from the two inputs
comp --> Compare the output from modulo (if equal 0 the output of compare goes 1 else 0).
My control works comparing the input C (input C <= output_comp), if the comparison value is equal 1 I increment the signal div, after this i verify the value of the input flag, if is equal 1 i go to the finish state of the state machine that verify if the value of signal div is equal 2, if it is the output of control gets value 1, if not gets value 0 (1 - prime , 0 - not prime).
My problem is in the output of control block that stays always in 0. I've simulated all blocks separated and it seems to work correctly.
I believe the error is in the for_reg or in the control block, because the other blocks are simple and like I said before, its working correctly.
Below the simulation of the mod block:
PS.: I've used a state machine to create this block, when it gets on the final state automatically returns to the first state, so it's because of that the output stays always 0 and 3.
Below the codes from control and for_reg:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;
ENTITY verifica_primo_control IS
PORT (
i_CLK : IN STD_ULOGIC;
i_RST : IN STD_LOGIC;
i_C : IN STD_LOGIC;
i_FLAG : IN STD_LOGIC;
o_DOUT : OUT STD_LOGIC
);
END verifica_primo_control;
ARCHITECTURE arch_1 OF verifica_primo_control IS
TYPE state_type IS (s0, s1, s2, s3);
SIGNAL stateT : state_type;
SIGNAL w_AUX : integer;
BEGIN
PROCESS(i_CLK)
BEGIN
IF rising_edge(i_CLK) THEN
IF (i_RST = '1') THEN
stateT <= s0;
w_aux <= 0;
ELSE
CASE stateT IS
when s0 => IF (i_C = '1') THEN
stateT <= s1;
ELSE
stateT <= s3;
END IF;
when s1 => w_AUX <= w_AUX +1;
if (i_FLAG = '1') then
stateT <= s2;
else
stateT <= s0;
end if;
when s2 => IF (w_AUX = 2) THEN
o_DOUT <= '1';
ELSE
o_DOUT <= '0';
END IF;
when s3 =>
if (i_FLAG = '1') then
stateT <= s2;
else
stateT <= s0;
end if;
END CASE;
END IF;
END IF;
END PROCESS;
END arch_1;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;
ENTITY for_reg IS
PORT (
i_CLR : IN STD_LOGIC;
i_CLK : IN STD_ULOGIC;
i_X : IN UNSIGNED (7 downto 0); -- number input to verify if its prime
i_I : IN UNSIGNED (7 downto 0) ;
o_FLAG : OUT STD_LOGIC;
o_II : OUT UNSIGNED (7 downto 0)
);
END for_reg;
ARCHITECTURE arch_1 OF for_reg IS
signal w_AUX : unsigned (7 downto 0);
BEGIN
PROCESS(i_CLK)
BEGIN
IF rising_edge(i_CLK) THEN
IF (i_CLR = '1') THEN
o_II <= "00000000";
w_AUX <= "00000000";
o_FLAG <='0';
ELSIF (i_CLR ='0' AND i_I < i_X) THEN
w_AUX <= i_I;
o_II <= w_AUX + "00000001";
o_FLAG <='0';
ELSIF (i_CLR = '0' AND i_I = i_X) THEN
o_II <= i_I;
o_FLAG <= '1';
END IF;
END IF;
END PROCESS;
END arch_1;
Like i said before, i believe the error is in one of this two blocks, i believe with that codes is possible verify where is the error. If this is not enough to have the MCVE warn me that i will update the post with the the other codes that is necessary to verify the error.
I am using the quartus II simulator, so I don't have a testbanch for this, I put all the test signals manually.
I have this code for a Serial Adder in VHDL. I am trying to get it to work, but I keep on getting an error that says:
Errors found in VHDL File -
Line : 17, Error : Index constraint expected in the subtype indication
This error is referring to the line:
signal state, next_state : integer range 0 to 3;
I'm not sure why this is happening. Any help? Please find the full code below.
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(
start : in std_logic;
clk : in std_logic;
a_out : out std_logic_vector(3 downto 0)
);
end adder;
architecture behave of adder is
signal a, b : std_logic_vector(3 downto 0);
signal shift : std_logic;
signal Cin, Cout : std_logic;
signal sum_in : std_logic;
signal state, next_state : integer range 0 to 3;
begin
sum_in <= a(0) xor b(0) xor Cin;
Cout <= (Cin and a(0))or(Cin and b(0))or(a(0) and b(0));
a_out <= a;
process(state, start)
begin
case state is
when 0 =>
if start = '1' then shift <= '1'; next_state <= 1;
else shift <= '0'; next_state <= 2; end if;
when 1 => shift <= '1'; next_state <= 2;
when 2 => shift <= '1'; next_state <= 3;
when 3 => shift <= '1'; next_state <= 0;
end case;
end process;
process(clk)
begin
if clk'event and clk = '0' then
state <= next_state;
if shift = '1' then
a <= sum_in & a(3 downto 1);
b <= b(0) & b(3 downto 1);
Cin <= Cout;
end if;
end if;
end process;
end behave;
Try to replace your line in which you are getting error by:
signal state, next_state : integer is range 0 to 3;
If you are specifying range then you should use is range instead of range
I want to make a 4-Bit Adder and Subtractor with VHDL
I have created 1-Bit Full-Adder , XOR Gate ( for Subtract ) and a 4-Bit Adder as shown below :
Full-Adder :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY FullAdder_1_Bit IS
PORT(
X, Y : IN STD_LOGIC;
CIn : IN STD_LOGIC;
Sum : OUT STD_LOGIC;
COut : OUT STD_LOGIC
);
END FullAdder_1_Bit;
ARCHITECTURE Behavier OF FullAdder_1_Bit IS
BEGIN
Sum <= X XOR Y XOR CIn;
COut <= (X AND Y) OR (X AND CIn) OR (Y AND CIn);
END Behavier;
XOR Gate :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY XORGate IS
PORT(
X1, X2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END XORGate;
ARCHITECTURE Declare OF XORGate IS
BEGIN
Y <= X1 XOR X2;
END Declare;
4-Bit Adder :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Adder_4_Bit IS
PORT(
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COut : OUT STD_LOGIC
);
END Adder_4_Bit;
ARCHITECTURE Structure OF Adder_4_Bit IS
COMPONENT FullAdder_1_Bit IS
PORT(
X, Y : IN STD_LOGIC;
CIn : IN STD_LOGIC;
Sum : OUT STD_LOGIC;
COut : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT XORGate IS
PORT(
X1, X2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL COut_Temp : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL XB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
B_0 : XORGate PORT MAP(Mode, B(0), XB(0));
B_1 : XORGate PORT MAP(Mode, B(1), XB(1));
B_2 : XORGate PORT MAP(Mode, B(2), XB(2));
B_3 : XORGate PORT MAP(Mode, B(3), XB(3));
SUM_0 : FullAdder_1_Bit
PORT MAP (A(0), XB(0), Mode, Sum(0), COut_Temp(0));
SUM_1 : FullAdder_1_Bit
PORT MAP (A(1), XB(1), COut_Temp(0), Sum(1), COut_Temp(1));
SUM_2 : FullAdder_1_Bit
PORT MAP (A(2), XB(2), COut_Temp(1), Sum(2), COut_Temp(2));
SUM_3 : FullAdder_1_Bit
PORT MAP (A(3), XB(3), COut_Temp(2), Sum(3), COut);
END;
and in my Main Codes , i have used those ( like Test-Bench ! ) :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY Add_AND_Sub IS
END Add_AND_Sub;
ARCHITECTURE Declare OF Add_AND_Sub IS
COMPONENT Adder_4_Bit IS
PORT(
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COut : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A, B : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL Mode : STD_LOGIC;
SIGNAL As, Bs, E, AVF : STD_LOGIC;
SIGNAL XA, XB, Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
Add : Adder_4_Bit
PORT MAP(XA, XB, Mode, Sum, E);
PROCESS(A, B, Mode)
BEGIN
As <= A(4);
Bs <= B(4);
XA <= A(3 DOWNTO 0);
XB <= B(3 DOWNTO 0);
CASE Mode IS
WHEN '0' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '1';
XA <= Sum;
AVF <= '0';
IF (E = '1') THEN
IF (XA = "0000") THEN
As <= '0';
END IF;
ELSE
XA <= (NOT XA) + "0001";
As <= NOT As;
END IF;
ELSE
XA <= Sum;
END IF;
WHEN '1' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '0';
XA <= Sum;
AVF <= E;
ELSE
AVF <= '0';
XA <= Sum;
IF (E = '1') THEN
IF (XA = "0000") THEN
As <= '0';
END IF;
ELSE
XA <= (NOT XA) + "0001";
As <= NOT As;
END IF;
END IF;
WHEN Others =>
--
END CASE;
END PROCESS;
END Declare;
The main scenario is to Model this algorithm :
but now i want to have output in XA and As
I Should use registers shown in algorithm such as "E" and "AVF"
there is one question :
we know port maps are continuously connected , so when i change Mode Value , Result ( Sum ) must change , is it True ?!
I have tried this code but i cant get output in XA , and there is no True result for sum values , i know there is some problem in my main code ( Process ) , but i cant find problems
please check that codes and tell me what goes wrong !
Edit :
Im using ModelSim and its simulation for testing my code , first i force values of "A", "B" and "Mode" then run to get result and wave
thanks ...
Your testbench add_and_sub makes no assignments to it's a and b, they're default values are all 'U's.
What do you expect when your inputs to adder_4_bit are undefined?
Look at the not_table, or_table, and_table and xor_table in the body of the std_logic_1164 package.
Also to be a Minimal, Complete, and Verifiable example your readers need both expected and actual results.
If you're actually simulating the testbench I'd expect it consume no simulation time and after some number of delta cycles during initialization show sum and e chock full of 'U's.
I haven't personally modified your testbench to determine if your adder_4_bit works, but if you provide it with valid stimulus you can debug it. It can be helpful to consume simulation time and use different input values.
Adding a monitor process to add_and_sub:
MONITOR:
process (sum)
function to_string(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
-- report "image_str = " & image_str;
return image_str;
end;
begin
report "sum = " & to_string(sum);
end process;
gives:
fourbitadder.vhdl:174:10:#0ms:(report note): sum = uuuu
one event on sum.
Add a process to cause events on a and 'b`:
STIMULUS:
process
begin
a <= "00000" after 10 ns;
b <= "00000" after 10 ns;
wait for 20 ns;
wait;
end process;
and we get:
(clickable)
We find we get an event on a and b but sum didn't change.
And the reason why is apparent in the case statement in the process. The default value of mode is 'U', and the case statement has choices for 0, 1 and:
when others =>
--
end case;
And the others choice results in no new value in mode.
Why nothing works can be discovered by reading the source of the body for package std_logic_1164, the xor_table, and_table, or_table. With mode = 'U' all your combinatorial outputs will be 'U'.
And to fix this you can assign a default value to mode where it is declared in the testbench:
signal mode : std_logic := '0';
With mode defined as a valid choice resulting in some action we note xa is now never defined causing the same issue:
(clickable)
And this is a problem in the process:
process(a, b, mode)
begin
as <= a(4);
bs <= b(4);
xa <= a(3 downto 0);
xb <= b(3 downto 0);
case mode is
when '0' =>
if ((as xor bs) = '1') then
mode <= '1';
xa <= sum;
avf <= '0';
if (e = '1') then
if (xa = "0000") then
as <= '0';
end if;
else
xa <= std_logic_vector(unsigned(not xa) + unsigned'("0001"));
as <= not as;
end if;
else
xa <= sum;
end if;
when '1' =>
if ((as xor bs) = '1') then
mode <= '0';
xa <= sum;
avf <= e;
else
avf <= '0';
xa <= sum;
if (e = '1') then
if (xa = "0000") then
as <= '0';
end if;
else
xa <= std_logic_vector(unsigned(not xa) + unsigned'("0001"));
as <= not as;
end if;
end if;
when others =>
--
end case;
Notice there are three places where xa is assigned, with no simulation time between them. There's only one projected output waveform value for any simulation time. A later assignment in the same process will result in the later value being assigned, in this case sum, which is all 'U's.
So how do you solve this conundrum? There are two possibilities. First you could not try and do algorithmic stimulus generation, assigning input to add explicitly with wait statements between successive assignments of different values. You can also insert delays between successive assignments to the same signal in the existing process, which requires a substantial re-write.
On a positive note the adder_4_bit and full_adder_1bit look like they should work. The problem appears to be all in the testbench.
I made some changes
I made a ALU unit as :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU IS
PORT(
--Clk : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Sel : IN STD_LOGIC;
AOut : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
AsO : OUT STD_LOGIC
);
END ALU;
ARCHITECTURE Declare OF ALU IS
COMPONENT Adder_4_Bit IS
PORT(
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COut : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL As, Bs, E, AVF : STD_LOGIC;
SIGNAL XA, XB, Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Mode : STD_LOGIC;
BEGIN
Add : Adder_4_Bit
PORT MAP(XA, XB, Mode, Sum, E);
PROCESS
BEGIN
As <= A(4);
Bs <= B(4);
XA <= A(3 DOWNTO 0);
XB <= B(3 DOWNTO 0);
CASE Sel IS
WHEN '0' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '1';
AVF <= '0';
WAIT ON Sum;
IF (E = '1') THEN
IF (Sum = "0000") THEN
As <= '0';
END IF;
ELSE
Sum <= (NOT Sum) + "0001";
As <= NOT As;
END IF;
ELSE
Mode <= '0';
WAIT ON Sum;
END IF;
AOut <= Sum;
AsO <= As;
WHEN '1' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '0';
WAIT ON Sum;
AVF <= E;
ELSE
Mode <= '1';
WAIT ON Sum;
AVF <= '0';
IF (E = '1') THEN
IF (Sum = "0000") THEN
As <= '0';
END IF;
ELSE
Sum <= (NOT Sum) + "0001";
As <= NOT As;
END IF;
END IF;
AOut <= Sum;
AsO <= As;
WHEN Others =>
--
END CASE;
END PROCESS;
END Declare;
and A Test Bench like this :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU_Test_Bench IS
END ALU_Test_Bench;
ARCHITECTURE Declare OF ALU_Test_Bench IS
COMPONENT ALU IS
PORT(
--Clk : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Sel : IN STD_LOGIC;
AOut : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
AsO : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL Xs, S : STD_LOGIC;
SIGNAL X, Y, O : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
ALU_PM : ALU PORT MAP(X, Y, S, O, Xs);
Main_Process : PROCESS
BEGIN
WAIT FOR 100 ns;
X <= "00010";
Y <= "11011";
S <= '0';
WAIT FOR 30 ns;
S <= '1';
WAIT FOR 30 ns;
WAIT FOR 100 ns;
X <= "01110";
Y <= "10011";
S <= '0';
WAIT FOR 30 ns;
S <= '1';
WAIT FOR 30 ns;
WAIT FOR 100 ns;
X <= "10011";
Y <= "11111";
S <= '0';
WAIT FOR 30 ns;
S <= '1';
WAIT FOR 30 ns;
END PROCESS;
END Declare;
As i say , i want to model the algorithm i posted in first post
there is some problem ...
for example when i simulate and run test bench , there is no output value in O and Xs !
I know the problem is in ALU and Test Bench
I changed ALU many times and tested many ways but all times some things goes wrong !
If you want to code that algorithm , which units you will create or at all what will you create ?! and how will you code that ?!
thanks for your help ...
how can i convert entity of bloch which takes 4 inputs to 2 inputs?
http://dl.dropbox.com/u/2879760/sample.PNG
A you see here i use three the same mux :( how to take in etykieta2 only two inputs?
code:
library ieee;
use ieee.std_logic_1164.all;
library work; --domyslnie zawieta moj pakiet
use work.mux_package.all;
entity glowny is
generic(
n : integer := 4;
k : integer := 2
);
port(
a, b, c, d,e,f,g,h : in std_logic_vector(n-1 downto 0);
s : in std_logic_vector(1 downto 0);
t : in std_logic_vector (1 downto 0);
y, x, z : out std_logic_vector(n-1 downto 0)
);
end glowny;
architecture multiplekser of glowny is
signal xx,yy,zz : std_logic_vector(n-1 downto 0);
for etykieta: mux use entity work.mux(arch_mux5);
for etykieta1: mux use entity work.mux(arch_mux6);
for etykieta2: mux use entity work.mux(arch_mux3);
begin
etykieta:
mux generic map (n=>n) port map (a=> a, b=>b, c=>c, d=>d,s=>s, y=>xx);
etykieta1:
mux generic map (n=>n) port map (a=> e, b=>f, c=>g, d=>h,s=>s,y=>yy);
etykieta2:
mux generic map (n=>n) port map (a=> yy , b=>yy, c=> xx, d=>xx, s=>t ,y=>zz);
end multiplekser;
packages
library ieee;
use ieee.std_logic_1164.all;
entity mux is
generic(
n : integer := 4
);
port(
a, b, c, d : in std_logic_vector(n-1 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(n-1 downto 0)
);
end mux;
-- przypisanie podstawowe - concurrent signal assigment
architecture arch_mux1 of mux is
begin
y(0) <= (a(0) and not(s(1)) and not(s(0)))
or (b(0) and not(s(1)) and s(0))
or (c(0) and s(1) and not(s(0)))
or (d(0) and s(1) and s(0));
y(1) <= (a(1) and not(s(1)) and not(s(0)))
or (b(1) and not(s(1)) and s(0))
or (c(1) and s(1) and not(s(0)))
or (d(1) and s(1) and s(0));
y(2) <= (a(2) and not(s(1)) and not(s(0)))
or (b(2) and not(s(1)) and s(0))
or (c(2) and s(1) and not(s(0)))
or (d(2) and s(1) and s(0));
y(3) <= (a(3) and not(s(1)) and not(s(0)))
or (b(3) and not(s(1)) and s(0))
or (c(3) and s(1) and not(s(0)))
or (d(3) and s(1) and s(0));
end arch_mux1;
-- przypisanie warunkowe - conditional signal assigment
architecture arch_mux2 of mux is
begin
with s select
y <= a when "00",
b when "01",
c when "10",
d when others;
end arch_mux2;
-- przypisanie selektywne - selected signal assigment
architecture arch_mux3 of mux is
begin
y <= a when (s = "00") else
b when (s = "01") else
c when (s = "10") else
d;
end arch_mux3;
architecture arch_mux4 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
case s is
when "00" => y <= a; -- czytamy y :=
when "01" => y <= b;
when "10" => y <= c;
--when "11" => y <= d;
y <= (others => '0');
when others => y <= d;
end case;
end process;
end arch_mux4;
architecture arch_mux5 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
if s ="00" then
y <= a;
elsif s="01" then
y <=b;
elsif s="10" then
y <=c;
else
y <=d;
end if;
end process;
end arch_mux5;
architecture arch_mux6 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
y<=(others=>'0');
if s ="00" then
y <= a;
end if;
if s ="01" then
y <= b;
end if;
if s ="10" then
y <= c;
end if;
-- if s ="11" then
-- y <= d;
-- end if;
end process;
end arch_mux6;
architecture arch_mux7 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
--w procesie jak najbardziej jest to prawidlowe, tylko warningi sa (LACHE - pamieci)
if s = "00" then
y <= a;
else
y <=(others => '0');
end if;
if s = "01" then
y <= b;
else
y <=(others => '0');
end if;
if s = "10" then
y <= c;
else
y <=(others => '0');
end if;
if s = "11" then -- zadziala tylko ten if bo jest sekwencyjnie ywkonywane i albo da 'd' albo 0000
y <= d;
else
y <=(others => '0');
end if;
end process;
end arch_mux7;
-- configuration conf_mux of mux is
--for arch_mux6
--end for;
--end conf_mux;
how can i convert entity of bloch
which takes 4 inputs to 2 inputs?
Do you mean make your input a to h and output x,y,z 2 bits wide rather than 4?
Just change the relevant generic, surely!