Coming from the world of MCUs, I create bootloaders so that customers can update the firmware.
How is this done with FPGAs and CPLD.
For FPGA:
Since the firmware is stored in external flash memory, does the FPGA image just write to it's external flash and then restart? But what happens if the new file is corrupt or the connection is removed while updating? Is there a way to make a default backup? In MCUs, the bootloader is never overwritten so the application can mess up anytime and the bootloader will still work.
Is there a separate dedicated non-volatile memory portion that is not re-configured on power up that you can load a bootloader in?
For CPLD:
Since the image is stored internally, do they have a way to configure themselves? How would one make a bootloader for a CPLD?
Other thoughts:
Maybe you can put an FTDI chip of some sort with GPIO that you can control from a PC app via USB. This way you can bitbang an SPI to load in a new image on the external flash? Anybody do that? That way the FPGA image can be corrupt or missing and still will be able to load a new image.
Note that i'm assuming that the FPGA or CPLD is alone on a board. Meaning there is not an MCU on the board to do all this.
Any insight as to how the industry achieves this task would be great.
FPGAs
There is no single common answer to this question. It is different for different FPGAs, and for different types of applications.
Some FPGAs have the capability to have two bitstreams in the external flash, so that if one bitstream is corrupted it will fallback to the second bitstream.
You must check the datasheet for your exact FPGA to find out if it has this kind of recovery feature, and exactly how it works.
Another common way to do it is to have a MCU sitting beside the FPGA, and let the MCU manage the bitstream update of the FPGA. Make it the MCUs responsibility to ensure there is a valid bitstream in the external flash.
Or, you can skip the external flash completely and make the MCU send the bitstream to the FPGA at every startup.
Some FPGAs, like the Xilinx ZYNQ, has a built-in hard processor. That processor can boot independent of the FPGA, so you write a normal bootloader for that processor, and make it the processors responsibility to update the FPGA bitstream.
If your application is a USB peripheral, then one nice way of handling it is to skip the flash memory, and make the USB driver on the PC load the bitstream to the FPGA at every startup.
Bitbanging it via a FTDIchip GPIO is not recommended as it would take a very long time. FTDIchip and other manufactuers have hardware support for both SPI and JTAG. With these you can do it quickly at each startup, with no bitbanging.
CPLDs
Typically no built-in recovery mechanism. (There may be exceptions)
CPLDs are very basic devices. If you want bitstream update capability, then it typically has to be done by an external MCU.
Normally you do not implement bitstream update function for CPLDs. You make your design error-free from the start instead.
Is there a way to make a default backup?
There is Intel MAX 10 family of fpga, it has on-chip configuration flash memory, and supports dual configuration. If anything wrong happens with one config, the other is still there and will be used as a fallback image.
But that's probably an exception, and not a typical case in fpga world.
In case the FPGA does not support dual configuration, and you are programming the FPGA directly ( not through a microcontroller), and somehow the new bitfile or the connection gets messed up, you have to program it again from scratch.
However, in Spartan 6, there are two ways to load the program directly to the FPGA :
1. This one is relatively fast and happens withing a couple of minutes. But if the setup gets messed up you have to start from scratch. This method is mostly used when you are doing minor modification (specially time related fine tuning) as the loading of the bitfile doesn't take up much time.
2. There's an external memory on which you load the program. The bitfile loaded on this memory remains unless you decide to explicitly re-write it. Loading the bitfile on this memory takes way more time (depending on the complexity of the code), but it stays there and you can load this code onto the FPGA.
Related
I have to program the FPGA using bootloader over ethernet connection.
My questions is that do I need to remove the inputs from the FPGA while programming its flash.
Regards
Uzmeed
I use the following Ethernet FPGA cores with necessary Ethernet functionality, flash programmer and more.
These cores supports this remote programming tool. The core works great and are very easy to use. Free to download.
Is the flash external or internal to FPGA? If the flash is external, most likely FPGA will have dedicated serial configuration interface. Now really depending on the sensitivity of other I/O and the speeds you are operating, if the board isn't designed right, fast edge rates on SPI interface can inject noise into other I/O channels(For example if there is an analog data line close by which is monitored through an ADC by FPGA). Highly unlikely that any of these will "damage" your FPGA, but if you care about data integrity on these I/O lines, even during flash is programmed, then that could be impacted. If this is an internal flash, obviously none of these would be an issue.
I am planning a project using three different uC: ATSAMC21N18, PIC18F4548 and a motor driver (not yet chosen). In total there will be 20-30 PCBs many of them are the same kind with the same firmware. For the main communication between the µC I have chosen CAN.
Usually, I flash the uC using a PICKIT with MPLab but with constant revisions and that many uC I am wondering if it is possible to flash the individual uC using CAN?
From my experience with the Arduino, it has a bootloader that enables the UART communication.
Can I include a bootloader that enables CAN on my chips? Do I have to write them myself? Are there existing tools to enable some functionality and write a bootloader to the chip?
I am unable to find literature on this topic.
I'm using the VC707 Fpga board which include a Virtex 7 Xilinx FPGA.
I want to transfer the Data from the DDR 3 memory to a PC via the PCIexpress.
Is there any tutorial that exist to do so?
I have been nreading this tutorial https://www.xilinx.com/support/documentation/boards_and_kits/vc707/2014_4/xtp207-vc707-pcie-c-2014-4.pdf
But it isn't that helpful
Thanks
Your question is missing some information, for example you don't tell us how the data gets into the DDR memory. I'll leave that for now.
You want to have an FPGA with DDR and PCIe. Both are very high speed interfaces and require a good understanding of electronics. You are using a commercial board so we can assume the board has been proven to work with DDR and PCIe.
You first need to make an FPGA with these interfaces. Thus you have to make a DDR block and and a PCIe block. Xilinx has done most of the work but you have to drive the tools to fill in the detail. That is what the tutorial is about.
Some Virtex-7 chips have a ready built PCIe block, but not all. What I have seen, none has a ready built DDR interface. There may be an similar tutorial how to make a DDR interface.
If you manage to work your way through that you have two individual blocks of logic. You then need the HDL skills to connect those up.
If you are lucky both blocks work. If, for some reason, they do NOT work the above mentioned knowledge of high speed interfaces and electronics must be applied as well as ho to debug an FPGA system.
Last but not least you have to write PCIe device drivers on your PC to access all what you have built.
My question about the tutorial was to assess your skills in FPGA and HDL. What you want to achieve requires experience and knowledge with FPGAs, HDL design and the Xilinx tools. If your have not worked with FPGA, HDL, Xilinx before you have two options:
First spend a few weeks/month to get more experienced in those fields.
Find somebody who has that experience already to do the most difficult work for (with?) you.
I have a usb modem with MT6272M chipset, can I take out its chipset and program it? I know that some ICs are programmable and some are not but I really want to program an IC without investing on arduino, rhasberry pi, or intel gallileo so trying to recycle electronic wastes.
Most of the ICs in the electronic waste are not programmable. Because they are specifically designed to do one job efficiently and that program is bound to the IC.
What you are searching is Programmable Integrated Circuit or Micro-controller chips. These are specifically designed to re-program again and again.
Anyhow if you find a specific Integrated Circuit from the waste,
First and most importantly, find its data-sheet (mostly available
in their manufacturer's website for free).
check whether is it a Programmable Integrated Circuit.
if yes, what is the hardware requirement to program it and build the
hardware circuit
write the program according to the specific requirements using
compatible libraries.
connect to the PC
Find the correct boot loader and upload it to the IC.
upload the program, which you have written, to the Programmable Integrated Circuit.
Test it
As you can see, you will need to build different hardware for different Programmable Integrated Circuit. So it is cheaper for you to buy arduino or raspberry circuit board. Then you can reprogram more chips using same board again and again plus the help of the community and the thousands of libraries.
Edit
If it is not mentioned in the datasheet whether you can program it or not , most probably it can't reprogram.
And other thing is that the main function of a modem is signal processing. For example, old cable modems are converting analog signals into digital signals. So they are not designed to reprogram or to do logical calculations. With my personal experience, you better start with a simple micro-controller and once you know the basics, you can go for higher level. Anyway I admire your idea to recycle the waste ICs.
I'm new to fpga programming, and I'm wondering how to make my fpga design distributable. Here's the scenario I have in mind. I have a network of computers, each deployed with an fpga based peripheral. I want to update the fpga design on the peripherals periodically. How do I accomplish this without spending a fortune on software licenses?
I have a small dev kit for an fpga that shipped with an executable to load example design files (it was an Altera fpga FYI). Does anyone know how I would create such an executable?
Some specifics:
My fpgas are Xilinx Spartan 6Es. I'm using Xilinx ISE for fpga development. The host computers are running debian linux.
Thanks for any and all advice!
If youre dealing with Altera: one computer would have the software tools and licenses needed to synthesize the project. Assuming all the FPGAs are the same model on each station/node, Quartus will generate an .sof file which you can copy and open from station to station. All you would need to do is download the Altera programmer tool (I believe you can download it separately from Quartus II) on each station which is free. Then upload the .sof to the board using the programmer, where you can permanently store it on the fpga prom using a technique similar to the following:
https://m.youtube.com/watch?v=ZrMe8JS7Ktk
However if you have Xilinx and Altera mix, Xilinx has .bit/xdl files, and uses another tool (impact) to upload their bitstreams. They can't be converted to and from bit and sof. So it's recommended that you probably stick to one make (Xilinx or Altera) and model based on your plans.
It looks like what you are looking for is how to make your FPGA's field upgradable. Assuming your FPGA is loading from an external memory such as an SPI flash chip, then you need to modify your design so that it is capable of writing to the SPI chip (or whatever) itself. This is most simply done by putting a register in your design which maps to the individual pins on the flash chip, and then "bit bang" the register from a connected computer. Assuming your FPGAs feed data into your own software running on the computer, then you would modify this software to have the functionality of manipulating this register to reflash the flash device. Obviously, if this goes wrong you bricked your device until it can be flashed again with the JTAG, but it provides a way for all the devices to get updated in the systems they operate without needing to buy a JTAG cable for every single station.
If you have Ethernet on your board you can use the remote programming tool from fpga-cores.
Then you can remote login to the network and program the FPGAs or mail the new config file to you customer and they run the programmer. This is how we remotely updates our boards.
Spartan 6 is supported. As a bonus you can also do some remote debugging with the remote logic analyzer.
Everything is free for non commercial use.