I am trying to understand how this data can be written to a SD, mounted on Sd card slot available in enclustra PM3 boards. I am using a ZYNQ PS7.
So is the above setting enough? any help is appreciated.
I am trying to write digital data using XADC on to this SD card.
My SD config is slightly different.
Edit:
I am sorry that was the wrong Zynq config.
Here is the right part for Mars PM3.
Related
I have a sd card which is connected on a microchip usb224x controller on im6qp processor based board.
SD signals are going to be converted in a USB dp and dm signal.
Now there are two use cases,
use case1: SD card is already inserted before power on,
sd 0:0:0:0: [sda] 249737216 512-byte logical blocks: (128 GB/119 GiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] No Caching mode page found
sd 0:0:0:0: [sda] Assuming drive cache: write through
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
Now if I remove SD card I don't get any kernel print which says that card is removed.
usecase2: SD card is inserted at running kernel.
No print comes that says that SD card is detected as sda.
In case 1 I can mount this SD card and access its contents.In case2 I cannot.
I have this question/confusion
Is user space responsible such as udev to tell if a device is present or not? I tried putting prints in many usb core files and none prints anything. However at the same time I am able to get interrupts on touch device that is using same usb bus but another channel.
I tried getting prints in usb functions in drivers/usb,storage and scsi subsysystem, but no observable prints came.
I tried enabling debugfs prints but I am getting no log even then and thats another issue which I am unable to resolve.
Main problem is I am getting no idea how and who initiates this change of removal and insertion, is it a low level kernel driver which looks for an interrupt and initiate the whole thing or udev such as /sbin/hotplug?
My kernel version is 4.9 and I am using build root for normal usecases, and also android O with same kernel. Same observation I am getting.
I am actually working on a device with the same chip and same kernel version. This would be better suited as a comment on your original post, however I don't have 50 points to do so yet (I am aware moderators).
Issues I am having:
I can detect add and remove uevents via udevadm monitor when the sd is not mounted.
When the sd is mounted I can only detect change events. Major/minor numbers I see are 8,0 and 8,1. Add and remove uevents come from minor number 1 (only while unmounted) while with minor 0 I only see change events (always, no difference if mounted) and which seem to be in a polling manner ("polling" behavior only seen with minor 0) (just going off looks. still looking at source to confirm it is actually polling). Quick insert and removal while mounted will only send one change uevent.
To answer your question '1':
from what I understand so far, these uevents are send from the kernel driver, specifically from the scsi mid-layer (drivers/scsi/scsi_lib.c). I have tracked that down to void scsi_evt_thread(struct work_struct *work) where it calls scsi_evt_emit() and eventually calls kobject_uevent_env() which from my understanding is responsible for blasting the uevent out to userspace via netlink.
If you are still debugging this, other information I figured I note along here is that scsi is a three-layered system. You have the top-most layer which for me is drivers/scsi/sd.c, mid-layer which I see as drivers/scsi/scsi.c and the bottom layer of drivers/usb/storage/usb.c (These are the main files for each layer from what I can tell. Learning as I go).
Still looking to figure out how a particular event is set on a specific scsi device. Is a scan of the bus triggered by interrupt or is there a thread which just continuously polls for changes (tdb)?
I want to build my own SOC based on the rocket chip without the use a ROCC(arm coprocessor). I checked this useful question: rocket chip on non zynq FPGA
I looked for some detailed documentation but I only found few slides describing the configurations without an actual tutorial.
Thus, I have three questions concerning the image below:
I managed to generate the overall verilog for the tinyConfig, but is it possible to generate only the Rocket Chip, HostIO/AXI Convertor and MemIO/AXIHP Convertor ? if yes how ?
Can a debug interface be added by the rocket Chip generator ?
Where can I change the RAM used in rocket chaip by a RAM of a specific FPGA vendor ?
The verilog generated by rocket-chip can be used in FPGA. You just need to replace the behav_srams.v with the RAM generated in vivado.
In system/Config.scala, You can add class WithJtagDTMSystem to your config to generate debug interface.
I am a newbie here, I used and have my hand on arduino, but now I got task of taking 3000 samples of waveform with 100MSPS with an adc.
As this was impossible with arduino and most of the controller I switch to FPGA,
And bought NUMATO MIMAS v2 (As it has on board 512Mb DDR RAM, which is capable of handling that much fast operation.)
And also bought AD9283 along with it as it has 100MSPS 8bit adc output.
I am using Xilinx ISE, and using Verilog(No specific reason for it).
My PROBLEM is I am unable to interface that inbuilt DDR ram and communicate with it.
Means there are no tutorial to write on that ram and read from it.
So can any one could help me on it?
I think you can read some file from Xilinx about Spartan 6.Like ug416 and ug388 .
Then you can make a Example Design (tutorial) for your board to simulation and communicate with DDR on real board.It is describe in ug416 page 67.You do not code as you creat a MIG IP.It creat a test file automatic.After you simulaion and verify on your board you will familiar with MIG IP.You shoud make sure these questions in this step.Like How many write/read path you will use?How to manage command path?How to addressing?What's the frequency do you need?And so on.
At last you can use MIG by your demand.If you just has only one stream data you will use MIG very easy.Like just use one write path and one read path.
Forgive my English.
I would like to build a (cheap) device to identify students at my university using their Student Card (called "ISIC").
My Phone (via its NFC reader on Android) tells me that these cards are :
NXP MIFARE DESFire / NXP MIFARE DESFire EV1
So far, I've tried hooking up an RC522 chip to an arduino board but wasn't able to communicate with the card (libraries are under development but I can't seem to get them working with this setup).
This is what I had in mind :
Raspberry pi 0
PN532 NFC/RFID controller breakout board
v1.6 by adafruit (which seems to be the best choice possible according to the nfc-tools wiki)
Before buying everything, here are my questions :
Has someone ever tried reading that kind of card with this board ?
Is there a cheaper and/or easier solution ?
Thanks a lot !
Depending on the situation I would recommend one of 2 options:
If you can firstly read all cards of your students and correlate the unique-UID (unique ID number for each contactless card) of each card with each student.
If you need to read the information of the card to get the student identification.
For Case 1: If your situation is "1", I would recommend that you just read the UID of each MIFARE DESFire EV1 and as far as you know the card UID of each student you would be able to identify them. Reading the UID of a MIFARE DESFire card is very easy and immediate with any reader or Android Smartphone; but before going forward with this option you should firstly check that the MIFARE DESFire cards are configured to have a non-Random UID.
To do so just read the UID of a single MIFARE DESFire card and check that the 1st byte of the UID:
If 1st byte = 0x08 -> Random UID (4 byte length)
If 1st byte = 0x04 -> You can use this proposal (7 byte length)
If "1st byte = 0x04" then you can just develop an Android application or a C application with a PC/SC reader or Raspberry PI very easily.
For Case 2:Then you need to understand how is the data stored in the MIFARE DESFire cards, if they have encription keys... You can develop applications with Android, Raspberry PI or desktop reader, but you'll need to understand better how does MIFARE DESFire EV1 works and of course the protection keys (if they have).
I hope it helps!
I am at moment having some problems storing an image generated in the PS part of my Zynq into the DDR3 of my board, and then read that image into the PL side of the board such that the VGA driver created there can
The PS creates a 640x480 image, which ideally i want to store in the Dram.
I've until now used the DMA to transfer the data back and forth and store it as in some way (not storing all pixels) into the block ram of my system. but that isn't a ideal solution and I know so too..
So my question is how do i access the DDR ram of my zynq board, i know it is located on the PS side, but cant seem to find any documentation explaining how it should be interfaced and so..
Usually on zynq you try to use Axi interface for the data.
You can use that by the interconnects and the adress.
In Vivado you have right of the block design diagram a tab called "Address Editor".
In my case a simple test application (axi dma with fifo) is used.
I configured the axi dma to the base address "0x4040_0000" Range of 64K so the High Adress is "0x4040_FFFF".
In The SDK you can access this memory via a C/C++ program.
Here is a short AXI DMA example:
axi dma example
This example was written for the zedboard but I tried it with the z-turn 7020 board and it worked in Vivado 2014.4 and 2016.1.
I hope this helps you.