I just started studying Genetic Algorithms and without looking at any existing GA in code, I wrote this simple program whose objective is to guess a number from a given range and that guessed number should match correctly with the expected number. I understand that GA basically evolves until it reaches its expected state.
What this program does is, it generates a random number, compares it with the correct number and adjusts its range after every failed guess and over a period of time it guesses the number correctly as the range gets narrower. Will this program be called a Genetic algorithm?
number_to_be_guessed = 10
attempt = 0
start = 0
end = 100
while True:
guessed_number = random.randint(start,end)
if guessed_number == number_to_be_guessed:
print("Number found, which is {}".format(guessed_number))
break
elif guessed_number > number_to_be_guessed:
end = guessed_number
else:
start = guessed_number
print("Attempt:{} -- Guessed Number:{} -- Start Value:{} -- End Value:{}"\
.format(attempt,guessed_number,start,end))
attempt += 1
Output
Attempt:0 -- Guessed Number:0 -- Start Value:0 -- End Value:100
Attempt:1 -- Guessed Number:27 -- Start Value:0 -- End Value:27
Attempt:2 -- Guessed Number:22 -- Start Value:0 -- End Value:22
Attempt:3 -- Guessed Number:15 -- Start Value:0 -- End Value:15
Attempt:4 -- Guessed Number:2 -- Start Value:2 -- End Value:15
Attempt:5 -- Guessed Number:6 -- Start Value:6 -- End Value:15
Attempt:6 -- Guessed Number:8 -- Start Value:8 -- End Value:15
Attempt:7 -- Guessed Number:9 -- Start Value:9 -- End Value:15
Attempt:8 -- Guessed Number:14 -- Start Value:9 -- End Value:14
Attempt:9 -- Guessed Number:12 -- Start Value:9 -- End Value:12
Attempt:10 -- Guessed Number:12 -- Start Value:9 -- End Value:12
Number found, which is 10
Here is a good summary.
I don't believe your solution can be called a genetic algorithm.
There are a few things that genetic algorithms tend to have:
There is a representation that facilitates "mutation". For example, if you can represent the state of your algorithm with a bit-word, and random permutations of the bit-word create valid altered states of your algorithm, then that resembles what you might see in a genetic algorithm.
The representation might also facilitate cross-breeding. So, using the bit-word example, if you can take half the bits from one solution and half from another and combine them; and that combination represents a valid state of the algorithm, then that resembles what you might see with a genetic algorithm.
Such algorithms tend to survive by natural selection. So you generally have a fitness function which determines how well you solution works. Solutions that are poor might be dropped. Solutions that are good might be mutated or cross-bred for the next iteration of testing.
Your algorithm does not do any of this.
There are few things you need to know to make a genetic/evolutionary algorithms
Define the problem
You have to know what do you want to get
Then you can start with developing Genetic algorithm
The code you posted is only brute force where you randomly take a number in a loop.
The real GA has some of the following steps:
Initialization of first generation
Evaluation of this generation
Selection of the parents
Genetic operations (mutations and crossover) (making children)
Evaluation of children
Taking some of them as a parents
Looping till your fitness function tells that your result is good enough
And there you have it. It is very hard to explain everything here. You will find it everywhere around the internet :)
Related
Similiarly to the question asked here, I face issues managing very large vectors in FPGA, and nothing really helped in the previous topic. I have a 2^15 bits wide sample, I want to make something similar to an bitwise autocorrelation of this sample by shifting-xoring-adding all the bits of this vector.
One of my constraints is a fast exectution time (less than 100ms with a 12MHz clock).
My way to do it for now is using an FSM in which one state is responsible for processing each iteration of the bitwise autocorrelation, and a following step comparing the current result to the minimum value so far (the minimum value reflecting the fundamental frequency of the sample). To do so, I use a for loop (not a big fan of this kind of structure usually...). Here is a piece of my code :
when S_BACF =>
count_ones :=(others=>'0');
for i in 0 to 32766 loop
count_ones := count_ones + (sample(i) xor sample((index+i) mod 32767));
end loop;
s_nb_of_ones_current <= count_ones;
current_state <= S_COMP;
when S_COMP =>
if index >= 19999 then
index <=0;
current_state <= S_END;
else
index <= index+1;
current_state <= S_BACF;
if s_nb_of_ones_saved > s_nb_of_ones_current then
s_nb_of_ones_saved <= s_nb_of_ones_current;
s_min_rank <= std_logic_vector(to_unsigned(index,15));
end if;
end if;
Sorry I don't define each signal/variable, but I think it is transparent enough. My index doesn't need to go beyond 20000 (for this application).
I think this way of processing data is quite efficient in registers use ("just" one vector of 2^15 bits and a 15-bits vector for the fundamental frequency).
In simulation, it works great. BUT, as expected, the synthesis fails, even for quite big targets. The for loop, though efficient in theory cannot be synthesised with such a big depth.
I imagined splitting my data into several smaller pieces, but the shifting-xoring operation through different smaller vectors is a nightmare.
I also thought about using the internal RAM of my FPGA to save my sample, in order to reduce the register usage, but it won't be effective against the for loop synthesis issue.
So, do any of you have a good idea for the synthesis to be successfull?
Let's suppose I have to test different bits on an std_logic_vector. would it be better to implement one single process, that for-loops for each bit or to instantiate 'n' processes using for-generate on which each process tests one bit?
FOR-LOOP
my_process: process(clk, reset) begin
if rising_edge (clk) then
if reset = '1' then
--init stuff
else
for_loop: for i in 0 to n loop
test_array_bit(i);
end loop;
end if;
end if;
end process;
FOR-GENERATE
for_generate: for i in 0 to n generate begin
my_process: process(clk, reset) begin
if rising_edge (clk) then
if reset = '1' then
--init stuff
else
test_array_bit(i);
end if;
end if;
end process;
end generate;
What would be the impact on FPGA and ASIC implementations for this cases? What is easy for the CAD tools to deal with?
EDIT:
Just adding a response I gave to one helping guy, to make my question more clear:
For instance, when I ran a piece of code using for-loops on ISE, the synthesis summary gave me a fair result, taking a long while to compute everything. when I re-coded my design, this time using for-generate, and several processes, I used a bit more area, but the tool was able to compute everything way way faster and my timing result was better as well. So, does it imply on a rule, that is always better to use for-generates with a cost of extra area and lower complexity or is it one of the cases I have to verify every single implementation possibility?
Assuming relatively simple logic in the reset and test functions (for example, no interactions between adjacent bits) I would have expected both to generate the same logic.
Understand that since the entire for loop is executed in a single clock cycle, synthesis will unroll it and generate a separate instance of test_array_bit for each input bit. Therefore it is quite possible for synthesis tools to generate identical logic for both versions - at least in this simple example.
And on that basis, I would (marginally) prefer the for ... loop version because it localises the program logic, whereas the "generate" version globalises it, placing it outside the process boilerplate. If you find the loop version slightly easier to read, then you will agree at some level.
However it doesn't pay to be dogmatic about style, and your experiment illustrates this : the loop synthesises to inferior hardware. Synthesis tools are complex and imperfect pieces of software, like highly optimising compilers, and share many of the same issues. Sometimes they miss an "obvious" optimisation, and sometimes they make a complex optimisation that (e.g. in software) runs slower because its increased size trashed the cache.
So it's preferable to write in the cleanest style where you can, but with some flexibility for working around tool limitations and occasionally real tool defects.
Different versions of the tools remove (and occasionally introduce) such defects. You may find that ISE's "use new parser" option (for pre-Spartan-6 parts) or Vivado or Synplicity get this right where ISE's older parser doesn't. (For example, passing signals out of procedures, older ISE versions had serious bugs).
It might be instructive to modify the example and see if synthesis can "get it right" (produce the same hardware) for the simplest case, and re-introduce complexity until you find which construct fails.
If you discover something concrete this way, it's worth reporting here (by answering your own question). Xilinx used to encourage reporting such defects via its Webcase system; eventually they were even fixed! They seem to have stopped that, however, in the last year or two.
The first snippet would be equivalent to the following:
my_process: process(clk, reset) begin
if rising_edge (clk) then
if reset = '1' then
--init stuff
else
test_array_bit(0);
test_array_bit(1);
............
test_array_bit(n);
end if;
end if;
end process;
While the second one will generate n+1 processes for each i, together with the reset logic and everything (which might be a problem as that logic will attempt to drive the same signals from different processes).
In general, the for loops are sequential statements, containing sequential statements (i.e. each iteration is sequenced to be executed after the previous one). The for-generate loops are concurrent statements, containing concurrent statements, and this is how you can use it to make several instances of a component, for example.
I have a problem - that I think I can solve with regular 'c' like operations
but I was wondering if there is a better way, something like 'regexp' for VHDL
the problem is that I have a string/collection of bits, "101010101010101" and I want to look for the pattern (with no overlapping) "1010" inside
what are my best options for attacking this problem?
edit : I'd like to mention that the input is parralel, all the bits at once and not in serial
it is still possible to implement this as an FSM - but it there a more efficient way?
If all you want to do is find a pattern within a vector, then you can just iterate over it. Assuming "downto" vectors:
process (vec, what_to_find)
begin
found <= 0;
for start in vec'high downto vec'low+what_to_find'length loop
if vec(start downto start - what_to_find'length) = what_to_find then
found <= start;
end if;
end for;
end process;
Depending on the sizes of your input and search vectors compared to the target device, this will be a reasonable or unreasonable amount of logic!
VHDL does not have builtin regex support, however what you are planning to solve is a pattern matching problem. Basically what you do is build a statemachine (which is what happens when evaluating a regular expression) and use it to match the input. The most simple approach is to check whether the first n bit match your pattern, then shift and continue. Longer, or more interesting patterns, e.g., incorporating quantifiers, matching groups etc. require a bit more.
There are numerous approaches to do that (try google vhdl pattern matching, it is used,e.g., for network traffic analysis), I even found one that would automatically generate the vhdl. I would guess, however, that a specialized hand-made version for your problem would be rather more efficient.
The there is no generally applicable VHDL solution for that kind of pattern
matching, but the solution should be driven by the requirements, since size and
speed can vary greatly for that kind of design.
So, if timing allows for ample time to do an all parallel compare and filtering
of overlapping patterns, and there is plenty of hardware to implement that,
then you can do a parallel compare.
For an all parallel implementation without FSM and clock, then you can make a
function that takes the pattern and collection, and returns a match indication
std_logic_vector with '1' for start of each match.
The function can then be used in concurrent assign with:
match <= pattern_search_collection(pattern, collection);
The function can be implemented with something along the lines of:
function pattern_search_collection(pat : std_logic_vector;
col : std_logic_vector) return std_logic_vector is
...
begin
-- Code for matching with overlap using loop over all possible positions
-- Code for filtering out overlaps using loop over all result bits
return result;
end function;
1) I have time series data and signals (indicators) that their value changes over time.
My question:
2) I need to do logical checking all the time, e.g. if signal 1 and 2 happened around the same time (were equal to a certain value e.g.=1) then I need to know the exact time in order to check what happened next.
3) to complicate things,e.g. if signal 3 happened in some time range after signal 1 and signal 2 were equal to 1, I would like to check other things.
4)The time series is very long and I need to deal with it segment by segment.
Please advice how to write it without inventing the wheel.
Is it recommended to write it in Matlab?, using a state machine? in C++?, using threads?
5) Does Matlab have a simulator ready for this kind of things?
How do I define the logical conditions in an efficient way?
6) Can I use data mining tools for this?
I saw this list of tools:
Data Mining open source tools
not sure where to start.
Thanks
The second and third question could be done like this in Matlab:
T = -range; % Assuming that t starts at 0.
for n = 1 : length(t)
if signal1(n) == 1 && signal2(n) == 1
T = t(n);
end
if t(n) - T < range && signal3(n) == 1
if % Conditions you want to get checked, could also be put in the previous if statement.
% Things you want to be executed if these coditions are met.
end
end
end
Using a lower level programming language like C++ would improve the rate at which it would be done. And if data is very long it could also reduce the amount of memory use by loading in an element of each array at the time.
Matlab has a simulator, called Simulink, but that is more meant for solving more complicated things, since you only conditionally want to do something.
I have two parameters fL and fV, both functions of T and P. If I make a function called func(T), which takes only T as input, then how do I go about implementing this step in Matlab:
Guess P
if |(fL/fV)-1|<0.0001 % where fL and fV are both functions of T and P
then print P
else P=P*(fL/fV)
Initially it is advised to guess the P in the beginning of the algorithm. All other steps before this involve formula calculation and doesn't involve any converging, so I didn't write all those formulas. The important thing to note is even though we take only T as input for our function, the pressure is guessed in the beginning of the code and is not part of any input by the user.
Thanks!
In order to "guess" P, you can either proceed using a) an educated guess or b) a random guess. So, for example if you were dealing with pressure in the day to day surroundings, 100kPa would be a reasonable guess. A random guess would mean initializing P to a random variable generated over a meaningful domain. So in my example, it could be a random variable uniformly distributed between 90kPa and 110kPa. Which of these approaches you choose depends on your specific problem.
You can code your requirements as follows
minP=90;maxP=110;
P=minP+(maxP-minP)*rand;%# a random guess between 90 & 100
<some code here where you calculate fL and fV
if abs(fL/fV-1)<0.0001
fprintf('%f',P)
else
P=P*fL/fV;
end