Quite a simple one, but I am pulling my hair out and need some fresh eyes. The problem is detailed below, originally I had the issue with a much larger package containing multiple items so stripped everything back to basics and still can't work it out...
thanks in advance
g
Simple code:
----------------------------------
-- LIBRARY_DECLARATIONS
----------------------------------
library STD;
use STD.standard.all;
----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
----------------------------------
-- PACKAGE_DECLARATION
----------------------------------
package Dummy_pkg is
component dummy_comp is
(
SIG_IN : in std_logic;
SIG_BI : inout std_logic;
SIG_OUT : out std_logic
);
end component dummy_comp;
end package TB_PHAS_FPGA_DUT_pkg;
package body TB_PHAS_FPGA_DUT_pkg is
end package body TB_PHAS_FPGA_DUT_pkg;
And this is the error I am getting from Modelsim (MS version):
vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd
# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016
# Start time: 13:49:21 on Oct 11,2018
# vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package Dummy_pkg
# ** Error: C:/_WorkDir/pkg_issue/Dummy_pkg.vhd(20): near "(": (vcom-1576) expecting END.
# End time: 13:49:21 on Oct 11,2018, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
You meant:
component dummy_comp is
port -- <--------------------
(
SIG_IN : in std_logic;
SIG_BI : inout std_logic;
SIG_OUT : out std_logic
);
end component dummy_comp;
Got it - I am missing 'port' from the component declaration....
always after you post... typical... sorry to waste time.
rgds, g.
Related
I am trying to get to grips with a simple Microblaze project, and have followed a tutorial I have found closely. I can synthesize the design in ISE successfully, but when I try and implement the design I get the following error:
ERROR::11 - Unexpected symbol 'MICROBLAZE', 'ADDRESS_MAP name' expected.
Line #1, File "ipcore_dir/microblaze.bmm".
ERROR:NgdBuild:989 - Failed to process BMM information ipcore_dir/microblaze.bmm
The file microblaze.bmm is generated by the microblaze core generator so I've not edited the contents.
The .bmm file generated with the microblaze core is:
ADDRESS_MAP microblaze MICROBLAZE-LE 100
ADDRESS_SPACE lmb_bram COMBINED [0x00000000:0x00001fff]
ADDRESS_RANGE RAMB16
BUS_BLOCK
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S9.The_BRAMs[0].RAMB16_S9_1 [31:24] INPUT = microblaze.lmb_bram_0.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S9.The_BRAMs[1].RAMB16_S9_1 [23:16] INPUT = microblaze.lmb_bram_1.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S9.The_BRAMs[2].RAMB16_S9_1 [15:8] INPUT = microblaze.lmb_bram_2.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S9.The_BRAMs[3].RAMB16_S9_1 [7:0] INPUT = microblaze.lmb_bram_3.mem;
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
And the microblaze is instantiated with this vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity microblaze_top is
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
UART_Rx : IN STD_LOGIC;
UART_Tx : OUT STD_LOGIC;
GPO1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
end microblaze_top;
architecture Behavioral of microblaze_top is
COMPONENT microblaze
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
UART_Rx : IN STD_LOGIC;
UART_Tx : OUT STD_LOGIC;
FIT1_Interrupt : OUT STD_LOGIC;
FIT1_Toggle : OUT STD_LOGIC;
GPO1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
INTC_IRQ : OUT STD_LOGIC
);
END COMPONENT;
begin
mcs_0 : microblaze
PORT MAP (
Clk => Clk,
Reset => Reset,
UART_Rx => UART_Rx,
UART_Tx => UART_Tx,
GPO1 => GPO1
);
end Behavioral;
I have run this command in the TCL console to include the microblaze in the synthesis.
source ipcore_dir/microblaze_mcs_setup.tcl
I have spent ages trawling various tutorials and I cannot fathom what the problem is. Can someone please give me a hint as to what is going wrong.
I don't seem to be able to find a way to contact the author of the tutorial.
I'm using ISE14.7 running in a virtual appliance.
(Edit - added the following aditional info)
I have taken a look in the console tab which appears to give some more info, compared to the Errors tab:
ERROR::37 - Illegal file or path name symbol 'MICROBLAZE'.
Line #5, File "ipcore_dir/microblaze.bmm".
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S9.The_BRAMs[0].RAMB16_S9_1 [31:24] INPUT = microblaze.lmb_bram_0.mem;
Looking closely ISE is not happy about microblaze.lmb_bram_0.mem; I'm not clear why though.
Below is a snapshot of the project Hierarchy:
And this is the MicroBlaze setup
I found this page, and the suggestion is that the naming in the bmm file might not be matching what you have in your design hierarchy. Can you confirm that? Since you have a name related error. microblaze might be invalid.
As you have updated your answer, it is visible that the hierarchical design name for it is in fact msc_0. Updating your bmm file with the correct naming would resolve the issue!
I'm using ISE 14.7 , synplify pro 2013.03 and modelsim 10.2c; now I having a problem about keeping a signal's name after synthesis and place&route in ISE and synplify. I used attribute keep and keep_hierarchy in XST,and syn_keep in synplify pro,but some reg was modified in XST after place&route;and all of reg was modified
in synplify,It seems my attributes was ignored in these tools,my code is in follow,can you help me?
attribute keep : string;
attribute keep of wr_adr_ram_1,rd_adr_ram_1 : signal is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
I'm new to Eiffel and I'm trying to create a simple class called "Monomio", I have 3 features that are attributes and a feature that's a function. The problem is that I'm getting a syntax error, I compared it to other classes I found but can't find the error here. This is my code
class
MONOMIO
create
make
feature {NONE} -- Initialization
make
-- Initialization for `Current'.
do
end;
coeficiente: INTEGER;
-- El número que será el coeficiente del monomio
exponenteX: INTEGER;
-- El exponente de la variable X
exponenteY: INTEGER;
-- El exponente de la variable Y
evaluar(valX: INTEGER; valY: INTEGER): INTEGER is
do
Result := coeficiente*(valX^expX)*(valY^expY)
end;
end
And this is the error I'm getting:
Syntax error at line 28 in class MONOMIO
evaluar(valX: INTEGER; valY: INTEGER): INTEGER is
---------------------------------------------^
do
I hope anyone can help me with this. Thanks.
I think the problem is the keyword "is". This has been deprecated, and if you are compiling with standard syntax (as you will be by default), then it is an error.
Just remove "is".
The problem of "syntax error" as an uninformative error message is one I have long been complaining about. It is entirely fixable, and no compiler should use it.
I have the following architecture:
architecture datapath of DE2_TOP is
begin
U1: entity work.lab1 port map (
clock => clock_50,
key => key,
hex6 => hex6,
hex5 => hex5,
hex4 => hex4
);
end datapath;
I am getting the following error: Error (10481): VHDL Use Clause error at DE2_TOP.vhd(276): design library "work" does not contain primary unit "lab1" on the line: U1: entity work.lab1 port map (. Anyone know what is causing this?
You need to have compiled at least the entityfor lab1 before you compile DE2_TOP
I have written something small in verilog:
`define LW 6'b100011
`define SW 6'b101011
parameter [3:0]
i_fetch = 4'b0001,
decode_rr = 4'b0010,
mem_addr = 4'b0100,
alu_exec = 4'b1000;
and i am getting this error: Error: test.v(5): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax.
What I am doing wrong? I am using ModelSim XE III/Starter 6.4b - Custom Xilinx Version!
Your parameter statement has to be within a module:
module a_module ();
parameter a_parameter = 4;
endmodule
In fact, most stuff in verilog has to be within a module block.