ADC to RAM signal reconstruction (after send it to VGA) - vhdl

Question

I should reconstruct a wave from the ADC into the RAM and later send it to the VGA.
I wrote this module, but when I synthesize, vivado produces an error:[Synth 8-3380] loop condition does not converge after 2000 iterations.
The error refers to the while loop, but i don't understand the reason. Unfortunately, if I can't synthezise the module i don't understand if it works well.
This is the module:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Data_Elab is
Generic (
C: integer := 640; -- Colonne 640
R: integer := 480 -- Righe 480
);
Port (
--clk: in std_logic;
DRP_Data: in std_logic_vector(15 downto 0);
DRP_Ready: in std_logic;
RAM_addr: out std_logic_vector(17 downto 0);
RAM_Data: out std_logic;
RAM_en: out std_logic
);
end Data_Elab;
architecture Behavioral of Data_Elab is
signal data_reg: integer range 0 to 2**16;
--signal flag: std_logic;
begin
process(DRP_Ready, DRP_Data)
begin
if(DRP_Ready'event and DRP_Ready = '1') then
data_reg <= to_integer(unsigned(DRP_Data));
end if;
end process;
process(data_reg)
variable Cont_W: integer range 0 to C-1 := 0; -- contatore per spostamento tra colonne
variable Cont_i: integer range 0 to C := 1; -- contatore colonne
variable Cont_x: integer range 0 to R := 1; -- contaore per spostamento tra righe
variable Cont_R: integer range 0 to R := 0; -- contatore righe
begin
if(Cont_i <= C) then
if( data_reg <= (2**16/R)*Cont_x ) then
RAM_addr <= std_logic_vector(to_unsigned( (C*(R-Cont_x))+Cont_W, RAM_addr'length));
RAM_en<= '1';
RAM_Data <= '1'; -- pixel corrispondente alla forma d'onda (bianchi)
Cont_W := Cont_W+1;
Cont_i := Cont_i+1;
--Cont_R := Cont_R+1;
--Cont_x := 1;
while Cont_R < R loop
RAM_addr <= std_logic_vector(to_unsigned( (C*(R-Cont_x))+Cont_W, RAM_addr'length));
RAM_en<= '1';
RAM_Data <= '0'; -- pixel neri
Cont_R := Cont_R+1;
Cont_x:= Cont_x+1;
end loop;
Cont_R := 0;
else
RAM_addr <= std_logic_vector(to_unsigned( (C*(R-Cont_x))+Cont_W, RAM_addr'length));
RAM_en<= '1';
RAM_Data <= '0'; -- pixel neri
Cont_R := Cont_R+1;
Cont_x:= Cont_x+1;
end if;
else
RAM_en<= '0';
Cont_W := 0;
Cont_i := 1;
Cont_x := 1;
Cont_R := 0;
end if;
end process;
end Behavioral;
The module tries to write the full image from 640*480 pixel in the RAM block, in this way i can read later the values stored in the RAM and send them tothe VGA module.
Thank you.

Answer 1

I guess the synthesizer is not smart enough to know how many times the while loop would run, because it changes in every loop. I would recommend using a for loop instead.
for Cont_R in 0 to R-1 loop
RAM_addr <= std_logic_vector(to_unsigned( (C*(R-Cont_x))+Cont_W, RAM_addr'length));
RAM_en<= '1';
RAM_Data <= '0'; -- pixel neri
Cont_x:= Cont_x+1;
end loop;