What I need:
all: release debug
release: compile
debug: compile
compile:
if parent_target_name = release:
$(CXXFLAGS) = for rel
else: $(CXXFLAGS) = for deb
The problem:
How to check the name of the target which invoked the current target?
I've seen this question GNU Make get parent target name but it didn't help.
What you are probably looking for is Target-specific Variable Values. If you carefully read this section of the manual you'll see how they propagate to the prerequisites.
Just to illustrate how they work:
.PHONY: all release debug compile
all:
$(MAKE) release
$(MAKE) debug
release: CXXFLAGS = for rel
debug: CXXFLAGS = for deb
release debug: compile
#echo 'building $# with CXXFLAGS = $(CXXFLAGS)'
compile: a b c
#echo 'building $# with CXXFLAGS = $(CXXFLAGS)'
a b c:
#echo 'building $# with CXXFLAGS = $(CXXFLAGS)'
Demo:
$ make --no-print-directory all
make release
building a with CXXFLAGS = for rel
building b with CXXFLAGS = for rel
building c with CXXFLAGS = for rel
building compile with CXXFLAGS = for rel
building release with CXXFLAGS = for rel
make debug
building a with CXXFLAGS = for deb
building b with CXXFLAGS = for deb
building c with CXXFLAGS = for deb
building compile with CXXFLAGS = for deb
building debug with CXXFLAGS = for deb
Related
I've written simple calculator in C++, and decided to separate lexer+parser and actual "frontends" which can be GUI or command-line. Project structure looks like that:
src/
parser.hpp
parser.cpp
scanner.hpp
scanner.cpp
exceptions.hpp
term-calc.cpp
gui-calc.cpp
Makefile
Obviously parser and scanner should be compiled into object files separately, and term-calc and gui-calc separately. Furthermore I want to have debug builds and release builds,
so I imagine final project structure like that:
src/
...
obj/
debug/
parser.o
scanner.o
...
release/
parser.o
scanner.o
...
out/
debug/
term-calc
gui-calc
release/
term-calc
gui-calc
Makefile
I'm pretty new to Makefiles but this is what I came up with so far (I've ommited automatic dependency generation for now):
CXX := g++
CXXFLAGS := -std=c++17 -pedantic -Wall -Wextra -fno-rtti
SRCDIR := $(CURDIR)/src # sources
OBJDIR := $(CURDIR)/obj # objects
INCDIR := $(CURDIR)/inc # generated dependencies
OUTDIR := $(CURDIR)/out # executables
# target programs
TERM_CALC := term-calc
GUI_CALC := gui-calc
all: debug
# debug flags
debug: CXXFLAGS += -O0 -g -fsanitize=address
# debug objects and executables go into /debug subdirectory
debug: OBJDIR += /debug
debug: OUTDIR += /debug
# release flags
release: CXXFLAGS += -Os -ffunction-sections -fdata-sections -flto -fno-ident
release: LDFLAGS += -Wl,-gc-sections -s -flto
# release objects and executables go into /release subdirectory
release: OBJDIR += /release
release: OUTDIR += /release
# common objects
OBJECTS := $(OBJDIR)/scanner.o $(OBJDIR)/parser.o
# target-specific objects
$(TERM_CALC): OBJECTS += $(OBJDIR)/term-calc.o
$(GUI_CALC): OBJECTS += $(OBJDIR)/gui-calc.o
# TARGET_NAME is name of program to build
# ensure it is valid, if defined
ifdef TARGET_NAME
ifneq ($(TARGET_NAME),$(TERM_CALC))
ifneq ($(TARGET_NAME),$(GUI_CALC))
$(error Invalid target name '$(TARGET_NANE)')
endif
endif
endif
ifdef TARGET_NAME
# how to build target program
$(TARGET_NAME): $(OUTDIR)/$(TARGET_NAME)
$(OUTDIR)/$(TARGET_NAME): $(OBJECTS)
#mkdir -p $(OUTDIR)
$(CXX) $(CXXFLAGS) $(LDFLAGS) $(LDLIBS) $^ -o $#
endif
# how to build objects
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp
#mkdir -p $(OBJDIR)
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $< -o $#
# if TARGET_NAME is not specified, just compile objects
TARGET_NAME ?= $(OBJECTS)
debug : $(TARGET_NAME)
release : $(TARGET_NAME)
# clean everything
clean:
$(RM) -r $(OBJDIR) $(OUTDIR) $(INCDIR)
.PHONY = all debug release clean
Unfortunately it absolutely does not work, while writing this makefile, I was getting many errors but even after fixing all of them as I thought, I still get:
Makefile:52: *** mixed implicit and normal rules: deprecated syntax
make: *** No rule to make target '/%.cpp', needed by '/root/cpp/calc/obj'. Stop.
I have a makefile that I want to be able to produce both a release build and a debug build. When I just run:
make
I want the CXXFLAGS to be:
-std=c++11 -Isrc/includes -c -Os
and when I run
make debug
I want the CXXFLAGS to be
-std=c++11 -Isrc/includes -c -g
I am trying to do this through he use of phony targets and appending the extra flags to the CXXFLAGS variable, however these extra flags are never being appended. why is it that make debug still produces:
g++ -std=c++11 -Isrc/includes -c src/file.cpp -o build/obj/file.o
and not the expected
g++ -std=c++11 -Isrc/includes -c -g src/file.cpp -o build/obj/file.o
when it is run?
contents of makefile:
vpath %.cpp src/macro
vpath %.cpp src/data_types
vpath %.hpp src/includes
vpath %.cpp src
CXX := g++
CXXFLAGS := -std=c++11 -Isrc/includes -c
LXX = g++
LXXFLAGS :=
BUILDDIR := build
OBJDIR := $(BUILDDIR)/obj
SRCS := $(notdir $(shell find -name '*.cpp'))
OBJS := $(patsubst %.cpp, $(OBJDIR)/%.o, $(SRCS))
all: release aval
aval: builddir $(OBJS) $(SRCS)
$(LXX) $(LXXFLAGS) $(OBJS) -o $(BUILDDIR)/aval
$(OBJDIR)/%.o: %.cpp
$(CXX) $(CXXFLAGS) $^ -o $#
.PHONY: release
release: CXXFLAGS += -Os
release: LXXFLAGS += -s -Os
.PHONY: debug
debug: clean db aval
.PHONY: db
db: CXXFLAGS += -g
.PHONY: builddir
builddir:
#mkdir -p $(OBJDIR)
.PHONY: clean
clean:
#rm -f -r build/obj/*.o
#rm -f build/avalanche
the issue with what you are doing is that you are editing the CXXFLAGS in the dependency list of a rule which won't work because of the way the make file is parsed.
Another way - and really easy, and saves you recursively calling make - which I don't see as particularly evil - but some do. Its certainly less complicated this way I find.
CXXFLAGS = defaults
ifneq (,$(findstring release,$(MAKECMDGOALS)))
CXXFLAGS += release
else ifneq (,$(findstring debug,$(MAKECMDGOALS)))
CXXFLAGS += debug
endif
all:
#echo CXXFLAGS = $(CXXFLAGS)
# Rules for release / debug. The `; #:` part means the body of the rule is empty (do nothing). It just "calls" the dependency rule `all`.
release: all ; #:
debug: all ; #:
So here we are looking at the command goals and "parsing them" to look for your options and add to the flags.
We also need rules for debug and release to call the build rule (which I am calling all for the moment).
Here is the output:
admin#osboxes:~/sandbox/flags$ make
CXXFLAGS = defaults
admin#osboxes:~/sandbox/flags$ make release
CXXFLAGS = defaults release
admin#osboxes:~/sandbox/flags$ make debug
CXXFLAGS = defaults debug
The approach you have chosen does not work, because
db: CXXFLAGS += -g
means that the variable CXXFLAGS is updated to include -g for the goal db, but no other goal. I.e. this change is not global like you intended it to be.
The following would be one way of implementing what you intended:
.PHONY: all release
# NOTE: must be first goal in Makefile to be default goal
all release:
$(MAKE) -f $(lastword $(MAKEFILE_LIST)) BUILD_CXXFLAGS="-Os" BUILD_LXXFLAGS="-s -Os" build
.PHONY: debug
debug:
$(MAKE) -f $(lastword $(MAKEFILE_LIST)) BUILD_CXXFLAGS="-g" BUILD_LXXFLAGS="-g" build
.PHONY: build
build: clean aval
CXX := g++
CXXFLAGS := $(BUILD_CXXFLAGS) -std=c++11 -Isrc/includes -c
LXX = g++
LXXFLAGS := $(BUILD_LXXFLAGS)
# ... and the rest of your original Makefile ...
With build implemented as a dummy echo, I get the following output from the above:
$ make -s
CXX '-Os -std=c++11 -Isrc/includes -c' LXX '-s -Os'
$ make -s all
CXX '-Os -std=c++11 -Isrc/includes -c' LXX '-s -Os'
$ make -s release
CXX '-Os -std=c++11 -Isrc/includes -c' LXX '-s -Os'
$ make -s debug
CXX '-g -std=c++11 -Isrc/includes -c' LXX '-g'
BTW: you also need to add -g to LXXFLAGS, otherwise you won't get a debug binary.
I am looking to write a makefile to automate the compiling of a project that I am working on where the files may, or may not, change in number. I also need to be able to quickly tell make to compile the files as a debug build or a release build (differentiated by a command line define). After some research, I came upon pattern rules and made one. Here is the code I have so far:
# Our folders
# ODIR - The .o file directory
# CDIR - The .cpp file directory
# HDIR - The .hpp file directory
ODIR = obj
CDIR = src
HDIR = inc
# Get our compiler and compiler commands out of the way
# CC - Our compiler
# CFNO - Our compiler flags for when we don't have an output file
# CF - Our compiler flags. This should be appended to any compile and should
# have the name of the output file at the end of it.
# OF - Object flags. This should be appended to any line that is generating
# a .o file.
CC = g++
CFNO = -std=c++11 -wall -Wno-write-strings -Wno-sign-compare -lpaho-mqtt3c -pthread -O2 -I$(HDIR)
CF = $(CFNO) -o
OF = -c
# Our project/output name
NAME = tls_test
# Set out Debug and Release settings, as well as any defines we will use to identify which mode we are in
# NOTE: '-D[NAME OF DEFINE]' is how you create a define through the compile commands
DEBUG = -DDEBUG -g
RELEASE = -DRELEASE
# Our two compile modes
# eval allows us to create variables mid-rule
debug:
$(eval DR = $(DEBUG))
release:
$(eval DR = $(RELEASE))
# Our compiling commands
all:
$(CC) $(CF) $(NAME) $(ODIR)/*.o
# NOTE: $# is the end product being created and $< is the first of the prerequisite
$(ODIR)/%.o: $(CDIR)/%.c
echo "$(CC) $(DR) $(OF) $(CF) $# $<"
The issue that I am having is with the order that I need things to run in. The command line call should tell make to use either debug or release, which sets a make variable, then call all. all should then run the pattern rule at the bottom before running the line currently in the all rule. So, how do I make a pattern rule a dependency and how do I call a rule from another rule?
Use target-specific variables
While not strictly necessary, separating your flags goes a long way in managing build options, you can then use target-specific variable appends to toggle the flags. While you're at it you might as well use the built-in variable names.
I've also added dependency generation (-MMD -MP) because it's always useful.
ODIR := obj
CDIR := src
HDIR := inc
SRCS := $(wildcard $(CDIR)/*.cpp)
OBJS := $(SRCS:$(CDIR)/%.cpp=$(ODIR)/%.o)
DEPS := $(OBJS:%.o=%.d)
CPPFLAGS := -I$(HDIR) -MMD -MP
CXXFLAGS := -std=c++11 -Wall -Wno-write-strings -Wno-sign-compare -pthread -O2
LDFLAGS := -pthread
LDLIBS := -lpaho-mqtt3c
NAME := tls_test
.PHONY: debug release clean
debug: CPPFLAGS+=-DDEBUG
debug: CXXFLAGS+=-g
release: CPPFLAGS+=-DRELEASE
debug release: $(NAME)
$(NAME): $(OBJS)
$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
$(OBJS): $(ODIR)/%.o: $(CDIR)/%.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $(OUTPUT_OPTION) $<
clean: ; $(RM) $(NAME) $(OBJS) $(DEPS)
-include $(DEPS)
I have a makefile building my project.
It builds fine when called with make, but if I try and do a make debug afterwards, it doesn't even attempt to create the debug output directory, which means the linking fails, even if I call make clean in between builds.
The debug build does work if I delete the "release" folder however.
Does anyone know why this happens?
Makefile
EXEC_DIR = ../../../../Bin/linux/release/
EXECUTABLE = $(EXEC_DIR)/prog
CC = g++
DEBUG = -g -D_DEBUG
...
CFLAGS = -Wall -c $(INCLUDE_DIRS) -std=c++11
LFLAGS = -Wall
...
all : $(EXECUTABLE)
debug : EXEC_DIR = ../../../../Bin/linux/debug/
debug : EXECUTABLE = $(EXEC_DIR)/prog
debug : CFLAGS += $(DEBUG)
debug : LFLAGS += $(DEBUG)
debug : $(EXECUTABLE)
$(EXECUTABLE) : $(OBJS) | $(EXEC_DIR)
$(CC) $(LFLAGS) $(OBJS) -o $(EXECUTABLE)
$(EXEC_DIR) :
mkdir -p $(EXEC_DIR)
...
clean :
-rm *.o *~
So what you're doing is creating a Target Variable, which is only effective in the scope of the debug recipes (not its sub-recipes). What you likely want to do is have lines as follow:
ifeq ($(filter debug,$(MAKECMDGOALS)),debug)
EXEC_DIR = ../../../../Bin/linux/debug/
OBJ_DIR = ../../../../Bin/linux/debug/objs
...
endif
and then prepend $(OBJ_DIR) to all of your object files. This gets around the not rebuilding source files that Etan was mentioning.
My directory has many files with similar names: test1.cpp, test2.cpp, test3.cpp, etc. I want to compile all test files into executables test1, test2, test3, etc. They don't have to be linked to each other.
CC = clang++
CXX = clang++
INCLUDES =
CFLAGS = -g -Wall $(INCLUDES)
CXXFLAGS = -g -Wall $(INCLUDES)
LDFLAGS = -g
LDLIBS =
.PHONY: default
default: test1 test2
test1:
test2:
Instead of specifying test1, test2, I want to use wildcards or pattern matching or something along those lines. How do I do this?
David Rodgriquez has the right idea: make has built-in rules that will handle this for you. However I would recommend using a makefile rather than setting variables in your environment, so you can easily perform the build as another user etc. where the environment is not set up properly. Also you can use a makefile to create the default target.
This is good enough:
CC = clang++
CXX = clang++
INCLUDES =
CFLAGS = -g -Wall $(INCLUDES)
CXXFLAGS = -g -Wall $(INCLUDES)
LDFLAGS = -g
LDLIBS =
.PHONY: default
default: $(basename $(wildcard test*.cpp))
That's all you need!