Makefile does not find target - makefile

I have the following Makefile, but it does not work. When I call
make html
I get a
make: *** No rule to make target `docs/index.html', needed by `html'. Stop.
error, even though I think I have defined it.
SRCDIR = source
OUTDIR = docs
RMD = $(wildcard $(SRCDIR)/*.Rmd)
TMP = $(RMD:.Rmd=.html)
HTML = ${subst $(SRCDIR),$(OUTDIR),$(TMP)}
test:
echo $(RMD)
echo $(TMP)
echo $(HTML)
all: clean update html
html: $(HTML)
%.html: %.Rmd
echo $(HTML)
#Rscript -e "rmarkdown::render('$<', output_format = 'prettydoc::html_pretty', output_dir = './$(OUTDIR)/')"
update:
#Rscript -e "devtools::load_all(here::here()); microcosmScheme:::updateFromGoogleSheet(token = './source/googlesheets_token.rds')"
## from https://stackoverflow.com/a/26339924/632423
list:
#$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$#$$' | xargs
.PHONY: update clean cleanhtml all list
The variables seem to be correct:
15:21 $ make test
echo source/index.Rmd
source/index.Rmd
echo source/index.html
source/index.html
echo docs/index.html
docs/index.html
If I change it as follow it works, but the target points to the SRCDIR, but I want it to point to the OUTDIR:
RMD = $(wildcard $(SRCDIR)/*.Rmd)
HTML = $(RMD:.Rmd=.html)
# HTML = ${subst $(SRCDIR),$(OUTDIR),$(TMP)}
I am sure it is one small thing...

This rule:
%.html : %.Rmd
....
tells make how to build a file foo.html from a file foo.Rmd, or a file source/foo.html from a file source/foo.Rmd, or a file docs/foo.html from a file docs/foo.Rmd.
It doesn't tell make how to build a file docs/foo.html from a file source/foo.Rmd, because the stem that matches the pattern % is not the same.
If you want to write a pattern for docs/foo.html to be built from source/foo.Rmd, you have to write it like this:
$(OUTDIR)/%.html : $(SRCDIR)/%.Rmd
....
so that the part that matches the pattern % is identical.
ETA Some other notes: you should be using := with the wildcard function as it's much better performing. Also you shouldn't use subst here because it replaces all occurrences of the string which could break things if any of your .Rmd files contain the string source for example (e.g., source/my_source_file.Rmd. This is much better written with patsubst, as in:
RMD := $(wildcard $(SRCDIR)/*.Rmd)
HTML := $(patsubst $(SRCDIR)/%.Rmd,$(OBJDIR)/%.html,$(RMD))
Finally, you don't show what the clean target does but it's unusual to have the clean target depended on by all. Usually it's a separate target that is invoked only when you want it, like make clean.

Related

Makefile ifeq always true

I have the following Makefile target:
target1:
$(eval count_abc := $(shell grep -c "ABC" myFileA))
$(eval count_def := $(shell grep -c "DEF" myFileB))
echo $(count_abc)
echo $(count_def)
ifeq ($(count_abc),$(count_def))
echo "TRUE"
else
echo "FALSE"
endif
But the output is always TRUE, e.g.:
echo 22
22
echo 21
21
echo TRUE
TRUE
What am I doing wrong here? What I want is INSIDE the target do 2 greps and compare their outputs and do something or something else based on the result. Please note that the greps must be done within the target since myFileA and myFileB get created on the target before and don't exist at the beginning when running make.
Thanks,
Amir
The rule file for "make" is declarative in nature - the makefile defines rules and targets, and then the make program evaluate the rules, and decide which action to take based on the target. As a result, execution is not always in the order the lines are entered into the file.
More specifically, the "ifeq" is evaluated at the rule definition stage, but the actions for building the target (eval count_abc ...) are executed when the target is built. As a result, when the ifeq is processed, both count_abc and count_def are still uninitialized, expanded to empty strings.
For the specific case you described - building a target that will compare the grep -c output from the two files, you can try something like below, effectively using shell variables (evaluated when target is evaluated), and not make variables (which are mostly declarative, evaluated when makefile is read)
target1:
count_abc=$(grep -c "ABC" myFileA) ; \
count_def=$(grep -c "DEF" myFileB) ; \
echo $(count_abc) ; \
echo $(count_def) ; \
if [ "$count_abc" -eq "$count_def" ] ; then echo TRUE ; else echo FALSE ; fi
Disclaimer: I did not run the revised makefile, not having access to desktop at this time.

Writing out dependencies into a file using Make

I'm writing a Makefile for Verilog compilation (isn't important if you aren't familiar with it). The compiler command can either take compile units or a flat file that has the compile units 'in order'. For the latter case, I'd like to write a rule that will spit out a file that has the dependencies in the right order.
Let's assume a simple makefile below:
a.output:
<a.files>
b.output: a.output
<b.files>
c.output: d.output
<c.files>
d.output: d.input
<d.files>
What I'd like is a file that contains:
a.files
b.files
d.files
c.files
An idea I had was to have a variable in the recipe that can be appended to, like
a.output:
MY_FILES += <a.files>
but I don't think that will work in a recipe context. Does anyone have a decent solution to this problem?
Also, I'd like the Makefile to be parallel but obviously it won't work for this target. How can I specify disabling parallel execution for this specific target or set of targets?
EDIT Oct 8 2019
To make it simpler for a person not familiar with Make syntax to write dependencies, I've basically let them write out their intent using variables:
MODULES += module_a
module_a.prerequisites = module_b module c
module_a.other_var = some_string_a
MODULES += module_b
module_b.prerequisites =
module_b.other_var = some_string_b
I then use a define directive to generate the rules necessary for compilation (I was inspired by this example). This means I do have flexibility on what I can create. So, in the previous example, <a.output> is actually the target for module_a. This can be a PHONY target. <a.files> actually represents the variables (prerequisites and other_var in the example).
I'm sorry for the miscommunication but what I'm trying to do is write out all the target and dependent module_x.other_var in the right order for a given module. I hope that makes it clear.
I'm currently concatenating a file in the right order which is one of the solutions mentioned below. I was wondering if there's some other Make magic that I could apply.
In its simplest form, you can just echo the names to the file
OUTPUT_FILE = output.file
a.output:
echo "<a.files>" > $(OUTPUT_FILE)
b.output: a.output
echo "<b.files>" >> $(OUTPUT_FILE)
c.output: d.output
echo "<c.files>" >> $(OUTPUT_FILE)
d.output: d.input
echo "<d.files>" >> $(OUTPUT_FILE)
If these files are prerequisites then you can print each dep or target using the auto vars:
Print the target/goal
d.output: d.input
echo "$#" >> $(OUTPUT_FILE)
print the first prerequisite
d.output: d.input
echo "$<" >> $(OUTPUT_FILE)
print all prerequisites
d.output: d.input
echo "$^" >> $(OUTPUT_FILE)
update for parallel build
Not pretty, can certainly improve this, but this will be safe for parallel builds. However as I say I think the echo method alone seems to work ok.
Also note this is not tested, so treat as pseudo code
OUTPUT_FILE = output.file
OUTPUT_FILE_A = output.file.a
OUTPUT_FILE_B = output.file.b
OUTPUT_FILE_C = output.file.c
OUTPUT_FILE_D = output.file.d
OUTPUT_FILES = $(OUTPUT_FILE_A)
OUTPUT_FILES += $(OUTPUT_FILE_B)
OUTPUT_FILES += $(OUTPUT_FILE_C)
OUTPUT_FILES += $(OUTPUT_FILE_D)
final: a.output b.output c.output d.output
echo "" > $(OUTPUT_FILE)
for file in "$(OUTPUT_FILES)" ; do \
cat $$file >> $(OUTPUT_FILE) ; \
done
a.output:
echo "<a.files>" > $(OUTPUT_FILE_A)
b.output: a.output
echo "<b.files>" > $(OUTPUT_FILE_B)
c.output: d.output
echo "<c.files>" > $(OUTPUT_FILE_C)
d.output: d.input
echo "<d.files>" > $(OUTPUT_FILE_D)

Writing version info to a file using Makefile

I am writing FW version to a file and then reading it while build I my project via Makefile. The SET rule writes the FW version info to the file and GET reads it from it.
When I do
make SET FW_VERSION_MAJOR=1 FW_VERSION_MINOR=2 FW_VERSION_PATCH=3 FW_VERSION_REVISION=4
make GET returns 1.2.3.4
But when I just do
make SET FW_VERSION_MAJOR=1
make GET returns 1...
What I want to achieve is if some one wants to do make SET and want to change only 1 or 2 or 3 parameters out of 4 in the FW version info then my version.h file should be able to retrieve the info left and shouldn't updated with an empty field.
FILE_CONFIG := path/to/version.h
.PHONY: SET GET
SET: VER_MAJOR ?= $(FW_VERSION_MAJOR)
SET: VER_MINOR ?= $(FW_VERSION_MINOR)
SET: VER_PATCH ?= $(FW_VERSION_PATCH)
SET: VER_REVISION ?= $(FW_VERSION_REVISION)
SET:
#echo '#define FW_VERSION_MAJOR $(FW_VERSION_MAJOR)\r\n#define
FW_VERSION_MINOR $(FW_VERSION_MINOR)\r\n#define FW_VERSION_PATCH
$(FW_VERSION_PATCH)\r\n#define FW_VERSION_REVISION $(FW_VERSION_REVISION)'
> $(FILE_CONFIG)
GET:
getnum = $(shell sed -n 's/.*$1 *\([0-9*]\)/\1/p' $(FILE_CONFIG))
FW_VERSION := $(call getnum,MAJOR).$(call getnum,MINOR).$(call
getnum,PATCH).$(call getnum,REVISION)
Not sure I fully understand what you try to achieve but there are several things to fix in your Makefile and examples:
your SET-specific variable definitions (VER_MAJOR...) are useless
your GET rule is empty
your example uses letters-only version numbers while your getnum macro retrieves digits-only version numbers
you must define the FW_VERSION_XXX if you want to use them in a rule when they are not passed on the command line
Try this, maybe:
FILE_CONFIG := version.h
.PHONY: SET GET
SET:
#echo '#define FW_VERSION_MAJOR $(FW_VERSION_MAJOR)\r\n#define FW_VERSION_MINOR $(FW_VERSION_MINOR)\r\n#define FW_VERSION_PATCH $(FW_VERSION_PATCH)\r\n#define FW_VERSION_REVISION $(FW_VERSION_REVISION)' > $(FILE_CONFIG)
GET:
#printf '%s\r\n' '$(FW_VERSION)'
getnum = $(shell sed -n 's/.*$1 *\([0-9*]\)/\1/p' $(FILE_CONFIG))
FW_VERSION_MAJOR := $(call getnum,MAJOR)
FW_VERSION_MINOR := $(call getnum,MINOR)
FW_VERSION_PATCH := $(call getnum,PATCH)
FW_VERSION_REVISION := $(call getnum,REVISION)
FW_VERSION := $(FW_VERSION_MAJOR).$(FW_VERSION_MINOR).$(FW_VERSION_PATCH).$(FW_VERSION_REVISION)
Demo:
$ make SET FW_VERSION_MAJOR=1 FW_VERSION_MINOR=2 FW_VERSION_PATCH=3 FW_VERSION_REVISION=4
$ make GET
1.2.3.4
$ make SET FW_VERSION_REVISION=5
$ make GET
1.2.3.5
Note: we can factorize a bit the FW_VERSION_XXX definitions and also the SET recipe:
FILE_CONFIG := version.h
VERSIONS := MAJOR MINOR PATCH REVISION
.PHONY: SET GET
SET:
#printf '' > $(FILE_CONFIG)
#$(foreach v,$(VERSIONS),$(call setnum,$(v)))
GET:
#printf '%s\r\n' '$(FW_VERSION)'
setnum = printf '\#define FW_VERSION_$1 $(FW_VERSION_$1)\r\n' >> $(FILE_CONFIG);
getnum = $(shell sed -n 's/.*$1 *\([0-9*]\)/\1/p' $(FILE_CONFIG))
$(foreach v,$(VERSIONS),$(eval FW_VERSION_$(v) := $(call getnum,$(v))))
FW_VERSION := $(FW_VERSION_MAJOR).$(FW_VERSION_MINOR).$(FW_VERSION_PATCH).$(FW_VERSION_REVISION)

Makefile: do operation on files with specific extension from a variable

I'm working on a Makefile which needs to be able to do the following:
From a user given variable, SRVS, containing file names, e.g.,
SRVS=Test1.java,test2.c,test3.c,test4.java,test5.c
produce a list of all files with a certain extension to be used by a foreach loop.
This list should not contain the extension anymore.
Currently, I can parse and get all the files into a usable list, but am unable to do so for an extension.
What I have:
$(foreach SRV, $(shell echo $(SRVS) | tr ',' ' '), \
CLASSPATH=$(SELF)/default_runtime javac $(UJ_DIR)/services/java/$(SRV).java && \
find $(UJ_DIR)/services/java/ -iname "$(SRV).class" -type f >> $(SELF)/files && \
) true
Which will take a list of SRVS and produce list usable by foreach and the code therein. For instance, the above example would result in "test1 test2 test3 test4 test5" to be used by the foreach loop
I'd like now to specify the extension, for instance .c, so that the above example would result in "test2 test3 test5".
Can you help me out?
First, you do not need to call shell (this is uselessly slow) because there are make built-in functions that do what you want. If, in the definition of variable SRVS you really cannot separate your file names with spaces (the standard make word separator) instead of commas, subst can do it for you. But there is a little trick because the comma is itself the arguments separator of make functions:
comma := ,
SRVS1 := $(subst $(comma), ,$(SRVS))
Next, filter is the make function that allows to select files by extension:
SRVS2 := $(filter %.c,$(SRVS1))
And finally, basename removes the suffix:
SRVS3 := $(basename $(SRVS2))
Demo:
$ cat Makefile
SRVS=Test1.java,test2.c,test3.c,test4.java,test5.c
comma := ,
SRVS1 := $(subst $(comma), ,$(SRVS))
SRVS2 := $(filter %.c,$(SRVS1))
SRVS3 := $(basename $(SRVS2))
all:
$(info SRVS1 = $(SRVS1))
$(info SRVS2 = $(SRVS2))
$(info SRVS3 = $(SRVS3))
$ make -q
SRVS1 = Test1.java test2.c test3.c test4.java test5.c
SRVS2 = test2.c test3.c test5.c
SRVS3 = test2 test3 test5
Or, all at once:
$ cat Makefile
TAGS := $(basename $(filter %.c,$(subst $(comma), ,$(SRVS))))
all:
$(info TAGS = $(TAGS))
$ make -q
TAGS = test2 test3 test5

gnu make: list the values of all variables (or "macros") in a particular run

How can I list the current value of all variables (also called macros) in a Makefile when running make?
E.g. if this is in the Makefile:
CUR-DIR := $(shell /bin/pwd)
LOG-DIR := $(CUR-DIR)/make-logs
Then I would like it to tell me:
CUR-DIR = /home/johv/src/test
LOG-DIR = /home/johv/src/test/make-logs
GNU make provides .VARIABLES
which holds all global variables' names.
However, this includes built-in variables(like MAKEFLAGS).
If you have to exclude built-in variables, some filtering like the following
might be needed.
The following makefile prints user-defined variables(CUR-DIR, LOG-DIR)
using info:
# Place this line at the top of your Makefile
VARS_OLD := $(.VARIABLES)
# Define your variables
CUR-DIR := $(shell pwd)
LOG-DIR := $(CUR-DIR)/make-logs
# Put this at the point where you want to see the variable values
$(foreach v, \
$(filter-out $(VARS_OLD) VARS_OLD,$(.VARIABLES)), \
$(info $(v) = $($(v))))
Thanks to #Ise Wisteria, condensed down, this shows all variables, useful for large projects with multiple makefiles (Buildroot).
$(foreach v, $(.VARIABLES), $(info $(v) = $($(v))))
output: BR2_GCC_TARGET_TUNE = "cortex-a8" ...
If you get an error like: insufficient number of arguments (1) to function 'addprefix' this project had some broken variables... I trimmed the list of variables to show, only with a prefix BR2_
$(foreach v, $(filter BR2_%,$(.VARIABLES)), $(info $(v) = $($(v))))
I ended up doing it like this:
gmake -pn | grep -A1 "^# makefile"| grep -v "^#\|^--" | sort | uniq > makevars.txt
which gives:
CUR-DIR := /home/johv/src/test
LOG-DIR := /home/johv/src/test/make-logs
MAKEFILE_LIST := Makefile
MAKEFLAGS = pn
SHELL = /bin/sh
VARS_OLD := [...]
gmake -pn is really verbose and looks kinda like this:
# environment
GNOME2_PATH = /usr/local:/opt/gnome:/usr:/usr/local:/opt/gnome:/usr
# automatic
#F = $(notdir $#)
# makefile
SHELL = /bin/sh
# default
RM = rm -f
It's also doable without saving all the .VARIABLES and filtering them out.
Moreover, if one of the original .VARIABLES was modified in your makefile, the two most voted answers won't catch it.
Check out $(origin) function. This target filters out and prints all the variables that were defined in a makefile:
print_file_vars:
$(foreach v, $(.VARIABLES), $(if $(filter file,$(origin $(v))), $(info $(v)=$($(v)))))
I get only a few excess variables this way: CURDIR SHELL MAKEFILE_LIST .DEFAULT_GOAL MAKEFLAGS.
One can replace file with environment or command line to print the respective kinds of variables.
There are a lot of good answers here, but you're going to have problems using $($(v)) if some of your variables are of the recursive flavor. This is why you should use $(value $(v)).
This variation cleans this up a little bit, sorts variables by name and makes the output a bit more readable.
dump:
$(foreach v, \
$(shell echo "$(filter-out .VARIABLES,$(.VARIABLES))" | tr ' ' '\n' | sort), \
$(info $(shell printf "%-20s" "$(v)")= $(value $(v))) \
)
Thanks to #kevinf for the great idea. I would suggest a minor change to prevent .VARIABLE itself from printing out in the variable list:
$(foreach v, $(filter-out .VARIABLES,$(.VARIABLES)), $(info $(v) = $($(v))))
Thanks to #kevinf for the foreach solution -- if one wants to export this list as a somewhat machine-readable file, one will have a hard time with uneven quotes or newlines when using echo or printf, since Make isn't able to quote the data correctly -- one needs to use the $(file ...) function to write the data to avoid sh/bash complaining about invalid syntax. For example, use this in your rule -- it prints variable name, definition and expanded value:
$(file > $(MAKEFILE_ENV_FILE),)
$(foreach v, $(.VARIABLES), \
$(file >> $(MAKEFILE_ENV_FILE),$(v)) \
$(file >> $(MAKEFILE_ENV_FILE), := $(value $(v))) \
$(file >> $(MAKEFILE_ENV_FILE), == $($(v))) \
$(file >> $(MAKEFILE_ENV_FILE),) \
)
(This will still not allow to always distinguish malicious variables with double newlines from two variables, for this one now add a sufficiently unique separator infront of each Makefile-generated newline just after each comma inside $(file >> NAME,TEXT))
Set MAKEFILE_ENV_FILE to some filename, e.g.:
MAKEFILE_ENV_FILE := $(abspath $(lastword $(MAKEFILE_LIST))).env

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