How to properly use -MD flag in Makefile - makefile

I'm trying to create a Makefile where make only recompiles necessary .cpp files.
By default, it works well if I edit .cpp, however, when I edit .h files, it just ignores the changes.
So I've read of -MD flag and its friend -MP (used to avoid bugs when typing make).
However, I can't seem to make it working, if I use -MMD, it works perfectly but I rely on system includes too as I'm writing a library too that is evolving along with the project. Thus, if I update the libary header and reinstall the library, typing make in the main project should recompiles files that includes the changed header.
When using -MMD flag, it - as expected - does not recompile the project, however, using -MD flag, it does recompile everything. In fact, -MD recompiles everything every time, even when nothing changed.
Here is a minimal project structure that reproduce the issue:
./Makefile:
all: build
re: clean build
build: build_lib install_lib build_client
build_lib:
$(MAKE) -C lib
$(MAKE) install -C lib
build_client:
$(MAKE) -C client
install_lib:
$(MAKE) install -C lib
.PHONY: clean
clean: clean_lib clean_client
clean_lib:
$(MAKE) clean -C lib
clean_client:
$(MAKE) clean -C client
./client/Makefile:
CC = g++
INC = -I../lib
CXXFLAGS = -Wall $(INC) -g -MD -MP
EXEC_NAME = ../test
src = $(shell find $(SOURCEDIR) -name '*.cpp')
obj = $(src:.cpp=.o)
LIBRARIES = -ltest_lib
LDFLAGS = -rdynamic $(LIBRARIES)
all: $(EXEC_NAME)
re: clean $(EXEC_NAME)
$(EXEC_NAME): $(obj)
$(CC) -o $# $^ $(LDFLAGS)
-include $(obj:.o=.d)
.PHONY: clean
clean:
rm -f $(obj) $(EXEC_NAME)
./lib/Makefile:
.PHONY : clean
CXXFLAGS= -fPIC -g -Itest_lib/include -MMD -MP
LDFLAGS= -shared
SOURCES = $(shell find $(SOURCEDIR) -name '*.cpp')
HEADERS = $(shell find $(SOURCEDIR) -name '*.h')
OBJECTS=$(SOURCES:.cpp=.o)
TARGET=libtest_lib.so
INC_FOLDER=test_lib/include
CUR_DIR = $(shell pwd)
all: $(TARGET)
install:
sudo rm -rf /usr/local/lib/libtest_lib.so && sudo ln -s $(CUR_DIR)/$(TARGET) /usr/local/lib/libtest_lib.so
sudo rm -rf /usr/local/include/test_lib && sudo cp -r $(INC_FOLDER) /usr/local/include/test_lib
clean:
rm -f $(OBJECTS) $(TARGET)
$(TARGET) : $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $# $(LDFLAGS)
-include $(OBJECTS:.o=.d)
./client/main.cpp:
#include "bar.h"
int main()
{
Bar b;
b.sayHello();
b.sayBye();
return 0;
}
./client/bar.h
#ifndef __BAR__
#define __BAR__
#include <test_lib/foo.h>
#include <iostream>
struct Bar : public Foo
{
Bar() {};
~Bar() {};
void sayBye() const {
std::cout << "Bye " << name << "..." << std::endl;
};
};
#endif
./lib/test_lib/include/foo.h
#ifndef __FOO__
#define __FOO__
struct Foo
{
const char *name;
Foo(const char *name = "world");
~Foo();
void sayHello() const;
};
#endif
./lib/test_lib/src
#include "foo.h"
#include <iostream>
Foo::Foo(const char *name) : name(name) {}
Foo::~Foo() {}
void Foo::sayHello() const
{
std::cout << "Hello " << name << " !" << std::endl;
}

Problem was that I copied the library headers all the time in /usr/local so the files got newer and the client make then thought every header of the library had changed.
A simple fix to this problem was to replace in the library Makefile the following line:
sudo rm -rf /usr/local/include/test_lib && sudo cp -r $(INC_FOLDER) /usr/local/include/test_lib
by
sudo rm -rf /usr/local/include/test_lib && sudo ln -s $(CUR_DIR)/$(INC_FOLDER) /usr/local/include/test_lib
On a side note, provided example is missing the removal of .d files on the clean rule.

Related

How to change the Makefile to create object file?

I am following a code from GitHub (https://github.com/dmalhotra/pvfmm).
There is a Fortran file in ./examples/src/example-f.f90. I have created a subroutine from this example-f.f90 so that I can make an object file out of it and can call this subroutine in our in-house code. The installation guide is given here (https://github.com/dmalhotra/pvfmm/blob/develop/INSTALL).
The Makefile to compile the example-f.f90 is as (https://github.com/dmalhotra/pvfmm/blob/develop/examples/Makefile):
ifndef PVFMM_DIR
PVFMM_DIR=./..
endif
-include $(PVFMM_DIR)/MakeVariables
ifndef CXX_PVFMM
$(error Cannot find file: MakeVariables)
endif
# FC=$(FC_PVFMM) # TODO: for now, FC must be provided by user
# CC=$(CC_PVFMM) # TODO: for now, CC must be provided by user
CXX=$(CXX_PVFMM)
CXXFLAGS=$(CXXFLAGS_PVFMM)
LDLIBS=$(LDLIBS_PVFMM)
RM = rm -f
MKDIRS = mkdir -p
BINDIR = ./bin
SRCDIR = ./src
OBJDIR = ./obj
INCDIR = ./include
TARGET_BIN = \
$(BINDIR)/example1 \
$(BINDIR)/example2 \
$(BINDIR)/example-sctl \
$(BINDIR)/fmm_pts \
$(BINDIR)/fmm_cheb
all : $(TARGET_BIN)
$(BINDIR)/%: $(SRCDIR)/%.f90
-#$(MKDIRS) $(dir $#)
$(PVFMM_DIR)/libtool --mode=link --tag=FC $(FC) $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -o $#
...
The MakeVariables can be found in the above link.
I changed this make file so that I can make an object file of example-f.f90 (subroutine, I converted as I told before to link it in our in-house code) and also other files in our in-house code and link at the end. The new makefile looks like:
ifndef PVFMM_DIR
PVFMM_DIR=./..
endif
-include $(PVFMM_DIR)/MakeVariables
ifndef CXX_PVFMM
$(error Cannot find file: MakeVariables)
endif
FC_PVMM = mpif90
FC = mpif90
FC=$(FC_PVFMM) # TODO: for now, FC must be provided by user
CC=$(CC_PVFMM) # TODO: for now, CC must be provided by user
CXX=$(CXX_PVFMM)
CXXFLAGS=$(CXXFLAGS_PVFMM)
LDLIBS=$(LDLIBS_PVFMM)
RM = rm -f
MKDIRS = mkdir -p
BINDIR = ./bin
SRCDIR = ./src
OBJDIR = ./obj
INCDIR = ./include
all : $(project_final)
project_final: $(project)
$(PVFMM_DIR)/libtool --mode=link --tag=FC mpif90 $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -o $#
project: example-f.o
cd ./src && $(MAKE)
example-f.o: $(SRCDIR)/example-f.f90
$(PVFMM_DIR)/libtool --mode=link --tag=FC mpif90 $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -c $#
...
Kindly note 'project: example-f.o
cd ./src && $(MAKE)' doing to make object files of our inhouse code. In src we have separate makefile to create object files for out in-house code.
But it gives me the following:
cd ./examples && make;
make[1]: Entering directory '/home/bidesh/Coding/FMM/pvfmm-1.3.0/examples'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/bidesh/Coding/FMM/pvfmm-1.3.0/examples'
How can I modify the makefile so that I can compile the whole code that includes example-f.f90 (subroutine) along with other subroutines (in-house code)?
Thanks a lot.

How to efficiently write a GNU makefile with several modules with an arbitrary number of dependencies in Fortran

My makefile currently looks like this:
#Source file locations
VPATH = :../AHMCodePara
#Compiler
CC = mpifort
#Debugging Flags
#Flags =
#Regular flags
Flags = -Ofast -mkl=sequential
# File name labels
FF =
DE =
Const =
OBJDIR = OBJ
# make object directory
$(OBJDIR):
-mkdir $(OBJDIR)
CC += -module $(OBJDIR)
#Object File List
Inputs =
Tools = $(OBJDIR)/$(Const)Inputs.o
Diag$(DE) = $(Tools)
PreAnalysis = $(Tools) $(OBJDIR)/Tools.o
DOSsetupPara$(DE) = $(PreAnalysis) $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o
$(Const)AHMRGv3 = $(Tools) $(OBJDIR)/Diag$(DE).o $(OBJDIR)/DOSsetupPARA$(DE).o
#Object File List
obj = $(OBJDIR)/$(Const)Inputs.o $(OBJDIR)/Diag$(DE).o $(OBJDIR)/Tools.o \
$(OBJDIR)/PreAnalysis.o $(OBJDIR)/DOSsetupPARA$(DE).o $(OBJDIR)/$(Const)AHMRGv3.o
# dependence files
$(OBJDIR)/%.o: %.f90 $(%)
# #$(%)
#-rm -f #<~
$(CC) -c $< -o $# $(Flags)
All: V3.e
# Target
V3.e: $(obj)
$(CC) $(Flags) -o $# $^
clean:
rm $(OBJDIR)/*.o $(OBJDIR)/*.mod
It used to be similar to this one:
LOC = ../../AHMCode/
CC = gfortran
#Debugging
#Flags = -O0 -g -fcheck=all -Wall -llapack
#Normal
Flags = -O3 -I/usr/lib/ -L/usr/lib/ -lblas -llapack
FF = _Old
IG = #IGNORE or nothing
TT = #TYPE or nothing
V3$(FF).e: Inputs.o Tools.o PreAnalysis.o DOSsetup$(IG).o Diag$(TT).o AHMRGv3_Manyruns.o
$(CC) $(Flags) AHMRGv3_Manyruns.o Diag$(TT).o DOSsetup$(IG).o PreAnalysis.o Tools.o Inputs.o -o V3$(FF).e
Inputs.o: Inputs.f90
$(CC) $(Flags) -c Inputs.f90
Tools.o: $(LOC)Tools.f90 Inputs.o
$(CC) $(Flags) -c $(LOC)Tools.f90
PreAnalysis.o: $(LOC)PreAnalysis.f90 Inputs.o Tools.o
$(CC) $(Flags) -c $(LOC)PreAnalysis.f90
DOSsetup$(IG).o: $(LOC)DOSsetup$(IG).f90 Inputs.o Tools.o PreAnalysis.o Diag$(TT).o
$(CC) $(Flags) -c $(LOC)DOSsetup$(IG).f90
Diag$(TT).o: $(LOC)Diag$(TT).f90 Inputs.o
$(CC) $(Flags) -c $(LOC)Diag$(TT).f90
AHMRGv3_Manyruns.o: AHMRGv3_ManyRuns.f90 DOSsetup$(IG).o Diag$(TT).o Inputs.o
$(CC) $(Flags) -c AHMRGv3_Manyruns.f90
clean:
rm *.o *.mod
The section I want to compare in these makefiles is the .o file definitions. In the second makefile, I wrote these all out by hand and it worked great. My intention with the second makefile was to do the same thing but more efficiently.
The problems arose with dependencies. When I initially made changes to my makefile, I didn't put any dependencies at all. This led to problems where I would update Inputs and the relevant files wouldn't recompile (e.g. Tools.o). This is as expected so I've been looking for ways to add dependencies in a creative and efficient way that forces the relevant files to recompile.
As you can see I tried creating variables with the same name as the .f90 and .o to use $(%). This seemed kinda janky (and I didn't really think it would work) but unfortunately didn't solve my problem.
As you can see from the original makefile, the dependencies don't follow any sort of pattern. As well you can see that I am compiling Fortran and I'm pretty sure that -gen-dep doesn't do anything and if it does I'm doing it wrong.
Existing questions on the subject have been very unhelpful since the majority uses C++ and that can be very different here.
EDIT: I "fixed" my problem. Its not the most efficient and doesn't automatically generate dependencies but I like it in that its not a lot of repetitive lines.
#Object File List
oInpt =
oTool = $(OBJDIR)/$(Const)Inputs.o
oPreA = $(oTool) $(OBJDIR)/Tools.o
oDOSs = $(oPreA) $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o
oDiag = $(oTool)
oMain = $(oTool) $(OBJDIR)/Diag$(DE).o $(OBJDIR)/DOSsetupPARA$(DE).o
obj = $(OBJDIR)/$(Const)Inputs.o $(OBJDIR)/Tools.o $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o \
$(OBJDIR)/DOSsetupPARA$(DE).o $(OBJDIR)/$(Const)AHMRGv3.o
# dependence files
$(OBJDIR)/$(Const)Inputs.o: $(oInpt)
$(OBJDIR)/Tools.o: $(oTool)
$(OBJDIR)/PreAnalysis.o: $(oPreA)
$(OBJDIR)/Diag$(DE).o: $(oDiag)
$(OBJDIR)/DOSsetupPARA$(DE).o: $(oDOSs)
$(OBJDIR)/$(Const)AHMRGv3.o: $(oMain)
$(OBJDIR)/%.o: %.f90
#-rm -f #<~
$(CC) -c $< -o $# $(Flags)
All: V3.e
# Target
V3.e: $(obj)
$(CC) $(Flags) -o $# $^
I just made multiple rules for each target. One a default rule that actually compiles the .o files and the other that specifies the dependencies for each .f90 file.

Make is not recognizing my library!

I am trying to create a program in C++ that utilizes the rudeconfig library.
I run make, and get this:
g++ -o Homework5_executable helloworld.o -lrudeconfig -L/home/j/je/jea160530/hw5/libs
/bin/ld: cannot find -lrudeconfig
collect2: error: ld returned 1 exit status
make: *** [Homework5_executable] Error 1
I know this is happening because make is not recognizing the rudeconfig library, however I have followed the instructions on the rudeconfig site for install correctly.
Here is the code:
Makefile
#
# Set up info for C++ implicit rule
CXX = g++
CXXFLAGS = -Wall
CPPFLAGS = -I/home/012/j/je/jea160530/hw5/include
#
# Set up any Linker Flags
LDFLAGS = -L/home/012/j/je/jea160530/hw5/libs
#
# Set up libraries needer for compilation
LDLIBS = -lrudeconfig
#
# We choose the project name. This is used in building the file name for the backup target
PROJECTNAME = JesseAlotto_Homework5
#
# We choose the source files to include and name the output
SRCS = helloworld.cc
#
# We choose the name of the executable to be created
EXEC = Homework5_executable
#
# NORMALLY DON'T NEED TO CHANGE ANYTHING BELOW HERE
# =================================================
#
OBJS = $(SRCS:cc=o)
all: $(EXEC)
clean:
rm -f $(OBJS) *.d *~ \#* $(EXEC)
Makefile: $(SRCS:.cc=.d)
# Pattern for .d files.
# =====================
%.d:%.cc
#echo Updating .d Dependency File
#set -e; rm -f $#; \
$(CXX) -MM $(CPPFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
# This is a rule to link the files. Pretty standard
# ================================================
$(EXEC): $(OBJS)
$(CXX) -o $(EXEC) $(OBJS) $(LDFLAGS) $(LDLIBS)
#echo Program compiled succesfully!
#
# Backup Target
# =============
backup: clean
#mkdir -p ~/backups; chmod 700 ~/backups
#$(eval CURDIRNAME := $(bash pwd))
#$(eval MKBKUPNAME := ~/backups/$(PROJECTNAME)-$(shell date +'%Y.%m.%d-%H:%M:%S').tar.gz)
#echo
#echo Writing Backup file to: $(MKBKUPNAME)
#echo
#tar -zcvf $(MKBKUPNAME) ./$(CURDIRNAME)
#chmod 600 $(MKBKUPNAME)
#echo
#echo Done!
#
# Include the dependency files
# ============================
-include $(SRCS:.cc=.d)
helloworld.cc
#include <string>
#include <iostream>
#include <fstream>
#include <tclap/CmdLine.h>
#include <map>
#include <stdlib.h>
#include <rude/config.h>
using namespace rude;
int main(int argc, char *argv[]){
std::string nextLine;
std::map<int, std::string> optionMap;
try{
std::cout << "hello world!";
//Command Line Variable
TCLAP::CmdLine cmd("CS3377.002 Program 5", ' ', "1.0");
//Switch Args
TCLAP::SwitchArg daemonSwitch("d", "daemon", "Run in daemon mode (forks to run as a daemon).", cmd, false);
//Unlabeled Value Args
TCLAP::UnlabeledValueArg<std::string> infileArg("infile", "The name of the configuration file. Defaults to cs3376dirmond.conf", true, "cs3376dirmond.conf", "config filename", false);
//Add leftover flags to cmdLine object
cmd.add(infileArg);
//Parse the command line
cmd.parse(argc, argv);
//Create an enumeratedlist for the mapping
enum flags {DAEMON, INFILE};
//Map keys and values to map
if (daemonSwitch.getValue()){
optionMap[DAEMON] = "1";
}
else{
optionMap[DAEMON] = "0";
}
optionMap[INFILE] = infileArg.getValue();
//Load input file
std::ifstream inputFile;
inputFile.open(optionMap[INFILE].c_str(), std::ios::in);
if(!inputFile){
std::cerr << "Error: no input file" << std::endl;
}
//============================================PARSE CONFIGURATION FILE==========================
Config config;
config.load("cs3376dirmond.conf");
//==============================================================================================
inputFile.close();
return 0;
} catch (TCLAP::ArgException &e) //catch any exceptions
{ std::cerr << "error: " << e.error() << " for arg " << e.argId() << std::endl;}
}
The error is caused by this command:
g++ -o Homework5_executable helloworld.o -lrudeconfig -L/home/j/je/jea160530/hw5/libs
not by make itself.
The error means that the linker isn’t finding librudeconfig.so in the library search path. From your comments, it turns out the library is named rudeconfig.so instead, so you need to specify
LDLIBS = -l:rudeconfig.so
instead of -lrudeconfig (which always expands to librudeconfig.so or librudeconfig.a).
Ideally, the library should be installed as librudeconfig.so...

Makefile which can generate all object files in a specific path

Somewhere I am going wrong !!
I am trying to generate the object files in ../bin/
But the below code generates in corresponding source file directory.
Below the code, which I am running.
Modified code:
LIB = $(BIN_DIR)/libutils.a
APP = $(BIN_DIR)/app
CC = gcc
AR = ar
CFLAGS = -Wall -g
LDFLAGS =
all: $(LIB) $(APP)
SRC = $(SRC_DIR)/add.c \
$(SRC_DIR)/sub.c
OBJ = $(SRC:.c=.o)
INCLUDES = -I$(INC_DIR)/
LIBS = -L../ -L/usr/local/lib -lm
LDFLAGS = -g
.SUFFIXES: .c
.c.o:
$(CC) $(INCLUDES) -c $(SRC_DIR)/$< -o $(BIN_DIR)/$#
$(LIB): $(OBJ)
$(AR) rcs $(LIB) $(OBJ)
$(BIN_DIR)/app: $(BIN_DIR)/test.o \
$(BIN_DIR)/t.o \
$(BIN_DIR)/libutils.a
$(CC) $(LDFLAGS) -o $# $^
clean:
rm -f $(LIB) $(BIN_DIR)/* $(SRC_DIR)/*.o *.o
Thank you :)
You still have the rule:
$(LIB): $(OBJ)
...
and OBJ is still src_dir/add.o src_dir/sub.o, so that's where Make will try to build these objects if your object rule works as intended. So, first step:
SRC = $(SRC_DIR)/add.c \
$(SRC_DIR)/sub.c
OBJ = $(SRC:.c=.o)
OBJ = $(patsubst $(SRC_DIR)/%.c,$(BIN_DIR)/%.o,$(SRC))
Now you'll find that your object rule,
.c.o:
...
doesn't work, because it expects to find the source file in the same place where the object file should go (i.e. $(OBJ_DIR)). So replace this rule with:
$(BIN_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(INCLUDES) -c $< -o $#
I notice that you have no provision for building $(BIN_DIR)/t.o and $(BIN_DIR)/test.o, but the app needs them. You should look into that.
Further refinements are possible, but this is a start.
Your SRC has a relative path, and your OBJ is just the SRC with the extension changed to. o
So OBJ will contain this:
../src/add.o
../src/sub.o
And there is where the .o will be created.
Make these changes and it will work:
SRC = add.c \
sub.c
.c.o:
$(CC) $(INCLUDES) -c ../src/$< -o ../bin/$#

Makefile dependency issue

I'm trying to compile an example code where I added a new file under a new directory but I keep getting a dependency problem.
I have added a file "ipc.c" under "/interface".
I have added the source file to "srcs" and also added the directory with "-I/interface".
The Makefile looks as follows:
#
# ======== Makefile ========
#
include ../products.mak
srcs = main_host.c interface/ipc.c
objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.o$(SUFFIX),$(srcs)))
libs = $(SYSLINK_INSTALL_DIR)/packages/ti/syslink/lib/syslink.a_$(PROFILE)
MAKEVARS = \
SYSLINK_INSTALL_DIR=$(SYSLINK_INSTALL_DIR) \
PKGPATH=$(PKGPATH)
all:
#$(ECHO) "!"
#$(ECHO) "! Making $# ..."
$(MAKE) $(MAKEVARS) PROFILE=debug SUFFIX=v5T togs2_host
$(MAKE) $(MAKEVARS) PROFILE=release SUFFIX=v5T togs2_host
install:
#$(ECHO) "#"
#$(ECHO) "# Making $# ..."
#$(MKDIR) $(INSTALL_DIR)/debug
$(CP) bin/debug/togs2_host $(INSTALL_DIR)/debug
#$(MKDIR) $(INSTALL_DIR)/release
$(CP) bin/release/togs2_host $(INSTALL_DIR)/release
clean::
$(RMDIR) bin
#
#
# ======== rules ========
#
togs2_host: bin/$(PROFILE)/togs2_host
bin/$(PROFILE)/togs2_host: $(objs) $(libs)
#$(ECHO) "##"
#$(ECHO) "## Making $# ..."
$(LD) $(LDFLAGS) -o $# $^ $(LDLIBS)
bin/$(PROFILE)/obj/%.o$(SUFFIX): %.h
bin/$(PROFILE)/obj/%.o$(SUFFIX): %.c
#$(ECHO) "###"
#$(ECHO) "### Making $# ..."
$(CC) $(CPPFLAGS) $(CFLAGS) -o $# $<
# ======== create output directories ========
ifneq (clean,$(MAKECMDGOALS))
ifneq (,$(PROFILE))
ifeq (,$(wildcard bin/$(PROFILE)))
$(shell $(MKDIR) -p bin/$(PROFILE))
endif
ifeq (,$(wildcard bin/$(PROFILE)/obj))
$(shell $(MKDIR) -p bin/$(PROFILE)/obj)
endif
endif
endif
# ======== install validation ========
ifeq (install,$(MAKECMDGOALS))
ifeq (,$(INSTALL_DIR))
$(error must specify INSTALL_DIR)
endif
endif
# ======== toolchain macros ========
ifeq (v5T,$(SUFFIX))
CC = $(CS_ARM_INSTALL_DIR)gcc -c -MD -MF $#.dep -march=armv5t
AR = $(CS_ARM_INSTALL_DIR)ar cr
LD = $(CS_ARM_INSTALL_DIR)gcc
CPPFLAGS = -D_REENTRANT -Dxdc_target_name__=GCArmv5T \
-Dxdc_target_types__=gnu/targets/arm/std.h
CFLAGS = -Wall -ffloat-store -fPIC -Wunused -Dfar= $(CCPROFILE_$(PROFILE)) \
-I. -I/interface $(addprefix -I,$(subst +, ,$(PKGPATH)))
LDFLAGS = $(LDPROFILE_$(PROFILE)) -Wall -Wl,-Map=$#.map
LDLIBS = -lpthread -lc
CCPROFILE_debug = -ggdb -D DEBUG
CCPROFILE_release = -O3 -D NDEBUG
LDPROFILE_debug = -ggdb
LDPROFILE_release = -O3
endif
I keep getting this error:
fatal error: opening dependency file bin/debug/obj/interface/ipc.ov5T.dep: No such file or directory
This is how the the products.mak looks like:
#
# ======== products.mak ========
#
DEPOT = /opt
BIOS_INSTALL_DIR = $(DEPOT)/bios_6_33_01_25
IPC_INSTALL_DIR = $(DEPOT)/ti/ipc_1_23_05_40
SYSLINK_INSTALL_DIR = $(DEPOT)/syslink_2_10_02_17
TI_C6X_INSTALL_DIR = $(DEPOT)/ti/ccsv5/tools/compiler/c6000
CS_ARM_INSTALL_DIR = $(DEPOT)/CodeSourcery/Sourcery_G++_Lite/bin/arm-none-linux-gnueabi-
XDC_INSTALL_DIR = $(DEPOT)/xdctools_3_23_00_32
PKGPATH := $(SYSLINK_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(BIOS_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$
# Use this goal to print your product variables.
.show-products:
#echo "BIOS_INSTALL_DIR = $(BIOS_INSTALL_DIR)"
#echo "IPC_INSTALL_DIR = $(IPC_INSTALL_DIR)"
#echo "SYSLINK_INSTALL_DIR = $(SYSLINK_INSTALL_DIR)"
#echo "TI_ARM_INSTALL_DIR = $(TI_ARM_INSTALL_DIR)"
#echo "TI_C6X_INSTALL_DIR = $(TI_C6X_INSTALL_DIR)"
#echo "CS_ARM_INSTALL_DIR = $(CS_ARM_INSTALL_DIR)"
#echo "XDC_INSTALL_DIR = $(XDC_INSTALL_DIR)"
# ======== standard macros ========
ifneq (,$(wildcard $(XDC_INSTALL_DIR)/bin/echo.exe))
# use these on Windows
CP = $(XDC_INSTALL_DIR)/bin/cp
ECHO = $(XDC_INSTALL_DIR)/bin/echo
MKDIR = $(XDC_INSTALL_DIR)/bin/mkdir -p
RM = $(XDC_INSTALL_DIR)/bin/rm -f
RMDIR = $(XDC_INSTALL_DIR)/bin/rm -rf
else
# use these on Linux
CP = cp
ECHO = echo
MKDIR = mkdir -p
RM = rm -f
RMDIR = rm -rf
endif
I'm not understanding the Makefile completely as it's a code example I'm simply expanding.
For the record: The error "fatal error: opening dependency file [...]: No such file or directory" can also be caused by a too long path. Happened to me on Cygwin/Windows with a path that was way over 200 characters (didn't check exactly).
Got it working.
Needed to add a rule to create the output directories.
So I added
ifeq (,$(wildcard bin/$(PROFILE)/obj/interface))
$(shell $(MKDIR) -p bin/$(PROFILE)/obj/interface)
endif
This makefile is pretty convoluted, so a certain amount of guesswork is required, but I think the trouble is that it doesn't know how to find interface/ipc.c. Try adding this line at the bottom and see if helps:
vpath %.c interface
If it doesn't, we can try some other things. (And if it does, I can suggest some ways to simplify the makefile.)

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