Define custom gmake function equivalent to multiple piped functions - makefile

Question

I'm trying to define a function that would to the work of $(patsubst %,$(OBJDIR)/%.o,$(basename $(ARG1)))
something like;
define getobj
$(1): $(patsubst %,$(OBJDIR)/%.o,$(basename $(1)))
endef
the context I'm trying to improve is:
OBJDIR = objects
TESTHNF_CPPS = testhnf.cpp timings.cpp LongModular.cpp VeryLong.cpp VeryLongModular.cpp squfof.cpp
TESTHNF_CS = mt19937int.c lip.c
TESTHNF_OBJS = $(patsubst %,$(OBJDIR)/%.o,$(basename $(TESTHNF_CPPS) $(TESTHNF_CS)))
TESTHNF_OBJS2 = $(getobj $(TESTHNF_CPPS) $(TESTHNF_CS))
Here, $(TESTHNF_OBJS2) remains empty. How should I write the function ?

Answer 1

Your getobj macro looks like you want to declare a rule (target: prerequisites). But the use you try to make of it looks like you try to assign the result of its expansion to a variable, which does not really make sense.
So, let's ignore the rule look and concentrate on your goal (as far as I understand it): define a macro that gets the basename of each word it is passed and substitutes it for $(OBJDIR)/<basename>.o. You were almost there:
getobj = $(patsubst %,$(OBJDIR)/%.o,$(basename $(1)))
should make it, where $(1) is the macro's parameter, a list of space-separated words. And you call it with the call make function:
TESTHNF_OBJS2 = $(call getobj,$(TESTHNF_CPPS) $(TESTHNF_CS))
The call make function substitutes $(1) for the $(TESTHNF_CPPS) $(TESTHNF_CS) parameter in the definition of getobj and returns the result. In your case it is equivalent to:
TESTHNF_OBJS2 = $(patsubst %,$(OBJDIR)/%.o,$(basename $(TESTHNF_CPPS) $(TESTHNF_CS)))
When TESTHNF_OBJS2 will be expanded the result will be:
objects/testhnf.o objects/timings.o ... objects/lip.o
Back to the rule look. If what you want instead is instantiate a make rule:
<basename>: $(OBJDIR)/<basename>.o
for each <basename> in your list, plus define a TESTHNF_OBJS variable listing all corresponding object files, what you can use is a combination of foreach, eval and call. But things are a bit more tricky because make expands the eval parameter once, instantiates the result as a make construct and expands it once more when parsing it as any regular make constructs. Double expansion must thus sometimes be escaped by doubling $ signs; this is not your case but it is better to keep this in mind when using such things.
OBJDIR = objects
TESTHNF_CPPS = testhnf.cpp timings.cpp LongModular.cpp VeryLong.cpp VeryLongModular.cpp squfof.cpp
TESTHNF_CS = mt19937int.c lip.c
TESTHNF_OBJS :=
# $(1): basename of one source file
define getobj
$(1): $(OBJDIR)/$(1).o
TESTHNF_OBJS += $(OBJDIR)/$(1).o
endef
$(foreach b,$(basename $(TESTHNF_CPPS) $(TESTHNF_CS)),$(eval $(call $(b))))
clean:
rm -f $(TESTHNF_OBJS)
As all this is rather complicated, and the benefits are quite low, it is probably better to stick with simpler constructs, easier to understand and maintain:
OBJDIR := objects
TESTHNF_CPPS := testhnf.cpp timings.cpp LongModular.cpp VeryLong.cpp VeryLongModular.cpp squfof.cpp
TESTHNF_CS := mt19937int.c lip.c
BASENAMES := $(basename $(TESTHNF_CPPS) $(TESTHNF_CS))
TESTHNF_OBJS := $(addprefix $(OBJDIR)/,$(addsuffix .o,$(BASENAMES)))
$(BASENAMES): %: $(OBJDIR)/%.o
clean:
rm -f $(TESTHNF_OBJS)
The rule is a static pattern rule.