Define "continue if error" policy directly in target dependencies - makefile

Question

Here's a simple Makefile with 4 targets (a, b, c and all). Target b can fail (represented here with exit 1).
a:
echo "a"
b:
exit 1
c:
echo "c"
all: a b c
When running make all, c is never printed as b fails and target c is consequently not run. But in my particular case, I want c to be run, even if b fails.
I'm wondering if there is a way to define the "continue if error" policy directly inside the dependencies of target all.
I know that the desired behaviour can be reached by :
running make -i all (--ignore-errors) or make -k all (--keep-going)
using a "recursive" make
prefixing failing command in b with - (like -exit 1)
running tasks separately with make a; make b || make c
but all of these options implies to modify targets a, b or c, or modify the way make all is called.
Is there a way to have the expected behaviour by just modifying the all target dependencies (something like all: a -b c, but that definition does not work, obviously)?
Additional requirement : make all should return with exit code 1 if b fails, even if c target succeeds.

Answer 1

If you want to run all recipes of a, -b, c even if the -<something> ones fail you can use a pattern rule for -<something> targets:
a c:
#echo "$#"
b:
#echo "$#"; exit 1
all: a -b c
-%:
-#$(MAKE) $*
Demo (with --no-print-directory for simpler output):
$ make --no-print-directory all
a
b
Makefile:5: recipe for target 'b' failed
make[1]: *** [b] Error 1
Makefile:10: recipe for target '-b' failed
make: [-b] Error 2 (ignored)
c
But if you also want to "remember" their exit status, things are a bit more difficult. We need to store the exit status somewhere, for instance in a file and reuse it for the all recipe:
a c:
#echo "$#"
b:
#echo "$#"; exit 1
all: a -b c
#exit_status=`cat b_exit_status`; exit $$exit_status
-%:
-#$(MAKE) $*; echo "$$?" > $*_exit_status
Demo:
$ make --no-print-directory all
a
b
Makefile:5: recipe for target 'b' failed
make[1]: *** [b] Error 1
c
Makefile:8: recipe for target 'all' failed
make: *** [all] Error 2
Hard-wiring the name of the potentially failing target in the recipe of all is not very elegant. But it should be quite easy to solve:
a b c:
#echo "$#"
d:
#echo "$#"; exit 1
all: a -b c -d
#for f in $(patsubst -%,%_exit_status,$(filter -%,$^)); do \
tmp=`cat $$f`; \
printf '%s: %s\n' "$$f" "$$tmp"; \
if [ "$$tmp" -ne 0 ]; then exit $$tmp; fi; \
done
-%:
-#$(MAKE) $*; echo "$$?" > $*_exit_status
.PHONY: clean
clean:
rm -f *_exit_status
Demo:
$ make --no-print-directory all
a
b
c
d
Makefile:5: recipe for target 'd' failed
make[1]: *** [d] Error 1
b_exit_status: 0
d_exit_status: 2
Makefile:8: recipe for target 'all' failed
make: *** [all] Error 2

Answer 2

While you can't transmit parameters through prerequisite names (or at least only if you change the prerequisites completely), you could employ target-specific variables. But the solution isn't exactly pretty, with an additional variable leading every recipe line:
CIE_DASH = $(if $(filter $#,$(CONTINUE_SET)),-)
all: a b c
all: CONTINUE_SET += b
a:
$(CIE_DASH)echo "a"
b: CONTINUE_SET += e
b: e
$(CIE_DASH)exit 1
e:
$(CIE_DASH)exit 1
c:
$(CIE_DASH)echo "c"