I implement a recipe in order to pass all the remaining string to the command, as example in this script:
Makefile
run:
# ./bin/run.sh $(filter-out $#,$(MAKECMDGOALS))
#echo $(filter-out $#,$(MAKECMDGOALS))
But when I run as example:
>make run my custom input params
my custom input params
make: *** No rule to make target `my'. Stop.
makefile try to execute also the remaining string so the error:
make: *** No rule to make target `my'. Stop.
How can I prevent this?
NB: As workaround I define a dummy recipe:
%:
#echo
So this will print an empty string instead of the error.
I want to avoid to do something like:
make run-example param="my custom param"
You can probably achieve what you want with a match-anything rule. Example (using a dummy printf recipe instead of a real one):
PARAMS := $(filter-out run,$(MAKECMDGOALS))
run:
#printf './bin/run.sh $(PARAMS)\n'
%:;
Demo:
$ make run my custom input params
./bin/run.sh my custom input params
make: 'my' is up to date.
make: 'custom' is up to date.
make: 'input' is up to date.
make: 'params' is up to date.
You can ignore the make: 'target' is up to date. messages or use the --quiet option (or --silent or -s):
$ make --quiet run my custom input params
./bin/run.sh my custom input params
If your Makefile is more complex than this, the match-anything rule could be a problem because it could catch other targets that you do not want to be caught. In this case make conditionals are an option:
ifeq ($(SECONDPASS),)
PARAMS := $(filter-out run,$(MAKECMDGOALS))
run:
#$(MAKE) --quiet $# PARAMS='$(PARAMS)' SECONDPASS=true
%:;
else
run:
#printf './bin/run.sh $(PARAMS)\n'
# other rules if any
endif
Finally, if the name of the first goal is not always the same, you can adapt this with:
GOAL := $(firstword $(MAKECMDGOALS))
PARAMS := $(filter-out $(GOAL),$(MAKECMDGOALS))
$(GOAL):
#printf './bin/$(GOAL).sh $(PARAMS)\n'
%:;
Or:
GOAL := $(firstword $(MAKECMDGOALS))
ifeq ($(SECONDPASS),)
PARAMS := $(filter-out $(GOAL),$(MAKECMDGOALS))
$(GOAL):
#$(MAKE) --quiet $# PARAMS='$(PARAMS)' SECONDPASS=true
%:;
else
$(GOAL):
#printf './bin/$(GOAL).sh $(PARAMS)\n'
# other rules if any
endif
Demo:
$ make --quiet nur foo bar
./bin/nur.sh foo bar
I don't think you should use a Makefile. You want to do your own parsing of the options, and that's more trouble to do in make.
If you're dead set on it, you could do this:
%:
#true
...which will avoid printing an empty line.
It would be better to do this in Bash, though. Here's one way you could do it:
#!/usr/bin/env bash
if [ $# -lt 1 ]; then
echo Not enough args
exit 1
fi
case "$1" in
"run")
shift
./bin/run.sh $#
;;
*)
echo "Command $1 not recognized"
exit 1
;;
esac
This seems easier and more extensible.
You can always pass / set ENV variables before executing make if you only want to pass variables to make or to a shell script.
MYPARAM1=123 MYPARAM2=456 make
OR using a subshell
(MYPARAM1=123; MYPARAM2=456; echo A=$MYPARAM1 B=$MYPARAM2; make)
(export MYPARAM1=123; export MYPARAM2=456; A=$MYPARAM1 B=$MYPARAM2; make) // exporting
You might also look at the bash-shell-special-parameters
Related
I have a makefile. I need to check the exit status of a command and the performing comparison, if exit status is 0 then perform some display action. But i am getting the same message if its success or failure for both the scenario.
Please find the below code and Help me what is the right way to do this:-
FILES = test1.sh test2.sh
manoj: $(FILES)
ls $(FILES)
$(eval exitstatus="$(shell echo $$?)")
#echo $(exitstatus)
ifeq (0,$(exitstatus))
$(error something going wrong..........)
endif
clean: pwd
Getting same output as :
testmake.mk:4: *** something going wrong........... Stop.
for both ifeq ifeq (0,$(exitstatus)) and ifneq ifeq (0,$(exitstatus))
I want to perform some action if the condition is success otherwise nothing want to do.
In the recipe shell commands are used, not make directives.
And when target's recipe is executed that means all its prerequisites do exist:
manoj: $(FILES)
#echo "$(FILES) do exist at this point."
Error : Makefile:12: *** recipe commences before first target. Stop.
My makefile:
objDir := obj
incDir := include
srcDir := src
binDir := bin
files := matrix palindrome encryption
define generateObject
#nasm -f elf32 -o $(objDir)/$(1).o $(srcDir)/$(1).asm
endef
object: $(addprefix $(srcDir)/,$(addsuffix .asm,$(files)))
#echo -n "Generating object files... "
$(foreach file,$(files),$(eval $(call generateObject,$(file))))
#echo "Done"
I read in a post that this could be due to unwanted whitespace/tab but i could not find any.
I tried cat -e -t -v Makefile and the output was :
objDir := obj$
incDir := include$
srcDir := src$
binDir := bin$
files := matrix palindrome encryption$
$
define generateObject$
^I#nasm -f elf32 -o $(objDir)/$(1).o $(srcDir)/$(1).asm$
endef$
$
object: $(addprefix $(srcDir)/,$(addsuffix .asm,$(files)))$
^I#echo -n "Generating object files... "$
^I$(foreach file,$(files),$(eval $(call generateObject,$(file))))$
^I#echo "Done"$
Your problem is use of the eval function. eval is used to parse make constructs, but you're passing it a shell command. Consider this line:
$(foreach file,$(files),$(eval $(call generateObject,$(file))))
Each time through the list you'll call generateObject with a filename. That will expand to a shell command; for example if file is matrix then call will expand to:
^I#nasm -f elf32 -o obj/matrix.o src/matrix.asm
Then you take that text string and pass it to eval which tries to read that as a makefile. Note that the text passed to eval must be a complete and valid makefile in itself; it's like you invoked make recursively and gave it this string as a makefile, except that the result of parsing are applied to the current makefile. You can't give eval just a part of a valid makefile (like one command line in a recipe) and have it insert that into the current makefile. Because that line by itself isn't valid, you get this error.
Instead of running eval on the results you want to concatenate them into one shell command. Try this:
define generateObject
nasm -f elf32 -o $(objDir)/$(1).o $(srcDir)/$(1).asm
endef
object: $(addprefix $(srcDir)/,$(addsuffix .asm,$(files)))
#echo -n "Generating object files... "
#$(foreach file,$(files),$(call generateObject,$(file)) && ) true
#echo "Done"
However, that's really not "the make way". You don't want to build multiple targets within a single rule: that defeats the main point of make which is that it only rebuilds the files that are out of date.
You should write your makefile like this:
object: $(files:%=$(objDir)/%.o)
$(objDir)/%.o : $(srcDir)/%.asm
#nasm -f elf32 -o $# $<
You don't need the generateObject variable, or call, or eval, or even foreach.
Let's consider this Makefile:
.SUFFIXES:
.DEFAULT_GOAL := all
out=foo
clean:
rm -f vars.mk
rm -f $(out)
vars.mk: vars.mk.default
#echo "Regenerating $#..."
cp $< $# # Let's assume the translation is much complex than a cp
-include vars.mk
ifeq ($(filter foo,$(FOO)),)
$(error FOO undefined)
endif
all: $(out)
$(out): vars.mk
echo "Cow says: I am not a $(FOO)." > $#
And the file vars.mk.default
FOO = foo bar
I would like to regenerate my targets if vars.mk.default is updated. Furthermore, as double check, one must check that foo exists in $(FOO).
How to force make to regenerate vars.mk if vars.mk.default is updated?
In other words, I would like this output:
$ make clean
$ sed 's/dog/cat/' vars.mk.default
$ make foo
Regenerating vars.mk...
echo "Cow says: I am not a cat" > all
$ make foo
make: Nothing to be done for 'all'.
$ sed 's/cat/dog/' vars.mk.default
$ make
Regenerating vars.mk...
echo "Cow says: I am not a dog" > all
$ rm vars.mak
$ make
Regenerating vars.mk...
echo "Cow says: I am not a dog" > all
To avoid failing if vars.mk doesn't exist, just check for it first:
ifeq ($(wildcard vars.mk),vars.mk)
ifeq ($(filter foo,$(FOO)),)
$(error FOO undefined)
endif
endif
My goal is to regenerate my targets if vars.mk.default is updated.
In this case make your targets depend on that file, but filter it out in the recipes, e.g.
foo.o : foo.cc vars.mk.default
$(COMPILE) $(filter-out vars.mk.default,$^)
In the case vars.mk does not exist, make fails on the ifeq and do not generates vars.mk.
Make is going to build vars.mk and restart, see How Makefiles Are Remade for more details.
So, to avoid that error, check first if FOO is defined with ifdef FOO.
A couple of things. First, you should put a - in front of the include to prevent a warning from popping up if the file does not exist:
-include vars.mk
This will not cause a fatal error if vars.mk is not generated, but because the vars.mk rule would fail in this case, you would get your error from there.
You can then check if $(FOO) contains foo from within a recipe:
checkForFoo: vars.mk
#[[ $(FOO) =~ .*foo.* ]] || false
all:checkForFoo
The recipe is only run after the vars.mk was generated and included, so it should only fail in the conditions you want.
Assume I have a build-target foo:
foo:foo.c
$(CC) $(CFLAGS) $(ARGS) -c foo.c -o foo
Now, ARGS is something that I pass on the command line:
$ make ARGS:=-DX=1 foo
So, I need to bypass make's cleverness, because the foo target does not only depend on which files have changed, but also on the value of ARGS.
Is there something in make to do this? My hack (see answer) doesn't seem to be the most elegant but it works. Anything better?
Here is a general solution to your specific problem.
You want to be able to depend on a variable as a prerequisite. That is, you can make it a prerequisite to any target in your makefile, and when the value of the variable changes, you rebuild those targets.
Here is a function that does that, you use this function to declare a variable to be dependable, and then you can use it as a prerequisite.
Note that if the variable is not used on the command line, it will still mean that variable still has a value, namely, the empty string.
define DEPENDABLE_VAR
.PHONY: phony
$1: phony
#if [[ `cat $1 2>&1` != '$($1)' ]]; then \
echo -n $($1) > $1 ; \
fi
endef
#declare ARGS to be dependable
$(eval $(call DEPENDABLE_VAR,ARGS))
foo:foo.c ARGS
$(CC) $(CFLAGS) $(ARGS) -c foo.c -o foo
In fact, we could omit the need for "declaration", and just write a similar function that will make all variables dependable by default. But I don't like that. I prefer that the users that modify makefiles I write, declare their intentions explicitly. It is good for them :)
My solution was to create a dummy phony target:
.PHONY:dummy
dummy:
#:
and have foo depend on dummy if ARGS is nonempty:
foo:foo.c $(patsubst %,dummy,$(ARGS))
Note on Mark's excellent answer
The bare necessities of Mark's answer are actually very simple. It really boils down to just:
.PHONY: phony
ARGS: phony
#if [[ `cat ARGS 2>&1` != '$(ARGS)' ]]; then echo -n $(ARGS) >ARGS; fi
The rest of his code is just to let you reproduce the recipe for other variable names without repeating yourself. Useful in practice, but the above version will help you see what's going on more easily.
In fact, my answer can even be made general (like Mark's) for any variable name, but in a less complicated way as follows:
.PHONY: phony
.ARG~%: phony
#if [[ `cat .ARG~$* 2>&1` != '$($*)' ]]; then echo -n $($*) >.ARG~$*; fi
Then you simply add .ARG~MYVARNAME as a dependency to any target to make that target depend on variable MYVARNAME.
Note that the dot in front of .ARG~% simply causes it to create a dependency-tracking file that is 'hidden' in linux.
So in your case, you would do:
foo: foo.c .ARG~ARGS
$(CC) $(CFLAGS) $(ARGS) -c foo.c -o foo
I don't understand how the other solutions are supposed to work. If the ARGS target is .PHONY or depends on a .PHONY, then it will always be run, right?
Here is my solution using the $(file) function in newer versions of gmake:
.PHONY: FORCE
define DEPENDABLE_VAR
$(1):
echo -n $($(1)) > $(1)
ifneq ("$(file <$(1))","$($(1))")
$(1): FORCE
endif
endef
#declare ARGS to be dependable
$(eval $(call DEPENDABLE_VAR,ARGS))
foo: foo.c ARGS
touch foo
And the result:
~/stuff/makevars> make foo ARGS=1
echo -n 1 > ARGS
touch foo
~/stuff/makevars> make foo ARGS=1
make: 'foo' is up to date.
~/stuff/makevars> make foo ARGS=2
echo -n 2 > ARGS
touch foo
~/stuff/makevars> make foo ARGS=2
make: 'foo' is up to date.
In the GNU make docs, '%' is documented to match "any nonempty substring". However, it seems it actually only matches non-empty substrings that do not contain whitespace. For example, say you do this:
mkdir /tmp/foo
cd /tmp/foo
echo 'int main() { return 0; }' > "test.c"
echo 'int main() { return 0; }' > "test space.c"
Now, you should be able to build these using GNU Make's built-in pattern rules:
anthony#Zia:/tmp/foo$ make "test"
cc test.c -o test
anthony#Zia:/tmp/foo$ make "test space"
make: *** No rule to make target `test space'. Stop.
The same problem happens when you write a makefile.
anthony#Zia:/tmp/foo$ rm test
anthony#Zia:/tmp/foo$ echo 'all: test test\ space' > Makefile
anthony#Zia:/tmp/foo$ make
cc test.c -o test
make: *** No rule to make target `test space', needed by `all'. Stop.
Even if you explicitly add in a %: %.c rule, the result is the same. But if you add in an explicit rule to the Makefile, like this, it works:
test\ space: test\ space.c
$(CC) -o "$#" "$<" # first char is tab, of course.
Is there a trick to get spaces to work with implicit rules?
edit
I've sent a bug report: http://lists.gnu.org/archive/html/bug-make/2011-06/msg00002.html
I don't believe so. The notion of a list of whitespace-separated tokens being passed around as a string is pretty deeply ingrained in make. Those lists are parsed and reparsed. There's a reason why spaces in directory and file names is considered bad practice in the UNIX world.
This is a kludge, but as of today, people still get given paths with spaces in sometimes.
Anyway, making a link instead of directly accessing the directory in the % rule works OK.
# GNU makefile
DIR_WITH_SPACE=/c/Users/me/My\ Code
# *** DOESN'T WORK ***
%.h : $(DIR_WITH_SPACE)/%.h
cp -v "$<" "$#"
fix:
ln -s $(DIR_WITH_SPACES) dir_fixed
# Does work :)
%.h : dir_fixed/%.h
cp -v "$<" "$#"