register Design in vhdl with modelsim - vhdl

Question

I'm trying to write register vhdl code in modelSim,My code is here:
Library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity reg_8Bit is
Generic(N:integer := 8);
port(clk,reset:in std_logic;
ctrl:in std_logic_vector(1 downto 0);
d:in std_logic_vector(n-1 downto 0);
q:out std_logic_vector(n-1 downto 0);
d2:out std_logic
);
end reg_8Bit;
-------------------------------
Architecture arch_8bit of reg_8Bit is
signal r_reg,r_next:std_logic_vector(n-1 downto 0);
begin
process(clk,reset)
begin
if(reset = '1') then
q <= (others => '0');
elsif(clk='1' and clk 'event) then
r_reg <= r_next;
end if;
end process;
with ctrl select
r_next <= r_reg when "00",
r_reg(n-2 downto 0) & d(i) when "10",
d(7) & r_reg(n-1 downto 1) when "01",
d when others;
q <= r_reg;
end arch_8bit;
I Want to create shift to right when ctrl = "01" and shift to left when
ctrl = "10" But I get just d(0) or d(7),How I can fixed it?

Answer 1

Problems with your code:
Signal q is multiple driven.
Your are resetting q but not r_reg
Improved code:
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity reg_8Bit is
generic(
N:integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
ctrl : in std_logic_vector(1 downto 0);
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0);
d2 : out std_logic
);
end entity;
-------------------------------
architecture arch_8bit of reg_8Bit is
signal r_reg : std_logic_vector(n-1 downto 0) := (others => '0');
begin
process(clk,reset)
begin
if(reset = '1') then
r_reg <= (others => '0');
elsif rising_edge(clk) then
if ctrl = "11" then
r_reg <= d;
elsif ctrl = "10" then
r_reg <= r_reg(r_reg'high - 1 downto r_reg'low) & d(0);
elsif ctrl = "01" then
r_reg <= d(7) & r_reg(r_reg'high downto r_reg'low + 1);
end if;
end if;
end process;
q <= r_reg;
end arch_8bit;
Other hints:
Don't use asynchronous resets.
Use rising_edge(clk) instead of clk'event ....
You can avoid the additional signal r_reg if you enabled VHDL-2008 in your tool.
In VHDL-2008, you can read back values from out ports.