My goal is to count the number of "01" sequences in iaI array.
I tried following code but it does not work as I assumed.
entity prob35 is
port (
iaI : in std_logic_vector (11 downto 0);
oaO : out std_logic_vector (2 downto 0)
);
end prob35;
architecture Behavioral of prob35 is
signal counter : integer := 0;
begin
process(iaI)
begin
for i in 1 to 11 loop
if (iaI(i-1)='1' and iaI(i)='0') then
counter<=counter+1;
end if;
end loop;
oaO<=conv_std_logic_vector(counter,oaO'length);
end process;
end Behavioral;
There is significant difference between signals and variables in vhdl. While the variable takes the value of assignment immediately, signal in sequential code (like process) are used to create flip-flops, which inherently do not immediately take the value of their assignment. You should use variable to achieve desired functionality here.
entity prob35 is
port (
iaI : in std_logic_vector (11 downto 0);
oaO : out std_logic_vector (2 downto 0)
);
end prob35;
architecture Behavioral of prob35 is
begin
process(iaI)
variable counter : unsigned(2 downto 0) := "000";
begin
counter := "000";
for i in 1 to 11 loop
if (iaI(i-1)='1' and iaI(i)='0') then
counter := counter + 1;
end if;
end loop;
oaO <= std_logic_vector(counter);
end process;
end Behavioral;
Related
I have this code in VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
entity Div is
Port ( Ain : in STD_LOGIC_VECTOR (6 downto 0);
Bin : in STD_LOGIC_VECTOR (6 downto 0);
Q : out STD_LOGIC_VECTOR (6 downto 0);
R : out STD_LOGIC_VECTOR (6 downto 0)
Rez : out std_logic_vector(13 downto 0));
end Div;
architecture Behavioral of Div is
begin
Proc1 : process (Ain, Bin) is
variable cnt : std_logic_vector(6 downto 0);
variable Atemp : std_logic_vector(6 downto 0);
begin
if (Ain < Bin) then
cnt := "0000000";
Atemp := Ain;
elsif (Ain = Bin) then
cnt := "0000001";
Atemp := (others => '0');
elsif (Ain > Bin) then
cnt := "0000001";
Atemp := (Ain - Bin);
while (Atemp >= Bin) loop
Atemp := (Atemp - Bin);
cnt := cnt + "0000001";
end loop;
end if;
Q <= cnt;
R <= Atemp;
Rez <= "0000000" & cnt;
end process Proc1;
end Behavioral;
and when I synt in Xilinx, I have this error message
Non-static loop limit exceeded
at that while loop.
When VHDL is synthesised, the synth tool needs to unwrap your loop to create a circuit. Because it has no idea what the Atemp or Bin are, other than they are 7 bit integers, it has to assume that Atemp and Bin could be static forever, and hence the loop never unrolls.
The problem with your code is that you used a while loop. Your HDL needs to describe a circuit, and a while loop generally doesn't. Instead of using a while loop, consider using a clock in your process and incrementing the counter by 1 on each clock. Circuits have no knowledge of time without a clock.
I have a priority encoding function that returns a vector containing a 1 at the position where the first 1 is found in the input vector. The function works as expected, unless I try to negate the input vector. Here's an example that demonstrates the unexpected behavior:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity tb IS
end tb;
architecture run of tb is
constant N : natural := 5;
function get_first_one_in_vec (vec_in: std_logic_vector) return std_logic_vector is
variable ret: std_logic_vector(vec_in'high downto vec_in'low);
begin
ret := (others => '0');
for i in vec_in'low to vec_in'high loop
if vec_in(i)='1' then
ret(i) := '1';
exit;
end if;
end loop;
return ret;
end get_first_one_in_vec;
signal a : std_logic_vector(N-1 downto 0);
signal abar : std_logic_vector(N-1 downto 0);
signal first_a : std_logic_vector(N-1 downto 0);
signal first_nota : std_logic_vector(N-1 downto 0);
signal first_abar : std_logic_vector(N-1 downto 0);
begin
process
begin
a <= "10100";
wait for 10 ns;
a <= "01011";
wait for 10 ns;
wait;
end process;
abar <= not(a);
first_a <= get_first_one_in_vec(a);
first_nota <= get_first_one_in_vec(not(a));
first_abar <= get_first_one_in_vec(abar);
end run;
To my understanding, first_nota should be the same as first_abar. However, my simulator (ModelSim - Intel FPGA Starter Edition 10.5b, rev. 2016.10) thinks otherwise, as you can see here:
What am I missing here?
This works OK:
function get_first_one_in_vec (vec_in: std_logic_vector) return std_logic_vector is
variable ret: std_logic_vector(vec_in'length downto 1);
variable inp: std_logic_vector(vec_in'length downto 1) := vec_in;
begin
ret := (others => '0');
for i in inp'right to inp'left loop
if inp(i)='1' then
ret(i) := '1';
exit;
end if;
end loop;
return ret;
end get_first_one_in_vec;
https://www.edaplayground.com/x/3zP_
Why does yours not work? Well, when you call your function with the not operator* as part of the expression:
first_nota <= get_first_one_in_vec(not a);
the numbering of the input to the function is changed to 1 to by the not operator. Why? Here is the code for the not operator and you can see why:
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
-- pragma built_in SYN_NOT
-- pragma subpgm_id 204
--synopsys synthesis_off
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
--synopsys synthesis_on
BEGIN
--synopsys synthesis_off
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
--synopsys synthesis_on
END;
---------------------------------------------------------------------
Anyway, this breaks your code (which starts scanning from the other end of the word).
One way of making function agnostic to the ordering of the numbering of its input is to normalise the inputs like this:
variable inp: std_logic_vector(vec_in'length downto 1) := vec_in;
Once you have done this, you're in control. So, instead of loops from 'high downto 'low, we can be more explicit and loop from 'right to 'left:
for i in inp'right to inp'left loop
not is an operator not a function. You don't need the brackets.
What I am trying to do is as follows:
I am taking few elements of an array, comparing them with a fixed value and trying to create a vector out of it.
Here is a piece of code:
architecture behav of main_ent is
...
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0);
...
process begin
sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&(ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A"));
....
end process;
...
This should give something like sel_sig_cmd = 1000 or may be 1011 etc. But this is not working. Is there any alternative to this code? cheers Tahir
This is because the = function in VHDL returns a boolean, not a std_logic.
In VHDL '93, there is no tidy way to do this, other than set each bit manually:
sel_sig_cmd(3) <= '1' when (ins_f_array(4) = x"3A") else '0'
sel_sig_cmd(2) <= '1' when (ins_f_array(3) = x"3A") else '0'
-- etc
but in VHDL 2008, there are the relational operators (?= ?/= etc), that return std_logic on compare. So your code becomes:
sel_sig_cmd <= ( (ins_f_array(4) ?= x"3A")
& (ins_f_array(3) ?= x"3A")
& (ins_f_array(2) ?= x"3A")
& (ins_f_array(1) ?= x"3A") );
The answer from Tricky is a good one to follow. However, if you want to implement it in a process, then the process can be rewritten as follows :
architecture behav of main_ent is
...
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0);
...
process(ins_f_array(4 downto 1)) begin
if ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&
(ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A")) then
sel_sig_cmd <= "XXXX" -- Enter your desired value
....
end process;
...
This process would be tedious though as it has to cover all the 16 possibilities of the "if condition".
Another implementation is to use an if condition for each bit as follows :
architecture behav of main_ent is
...
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0);
...
process(ins_f_array(4 downto 1)) begin
if (ins_f_array(4) = x"3A") then
sel_sig_cmd(3) <= "X" -- Enter your desired value
else
sel_sig_cmd(3) <= "X" -- Enter your desired value
end if;
-- Repeat for other bits
....
end process;
...
You can overload the "=" operator :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end entity;
architecture behav of tb is
function "=" (Left, Right: std_logic_vector) return std_logic is
begin
if (Left = Right) then
return '1';
else
return '0';
end if;
end function "=";
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array := (x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07",x"08");
signal sel_sig_cmd : std_logic_vector(3 downto 0);
begin
process (ins_f_array(1 to 4)) begin
sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3) = x"3A")&(ins_f_array(2) = x"3A")&(ins_f_array(1) = x"3A"));
end process;
process
begin
wait for 10 us;
for i in 0 to 8 loop
ins_f_array(i) <= std_logic_vector(unsigned(ins_f_array(i)) + 1);
end loop;
end process;
end architecture;
I have a question which is probably in 2 parts:
I am using a (nominally 32 bit) integer variable which I would like to write to an 8 bit UART as 4 bytes (i.e., as binary data)
i.e. variable Count : integer range 0 to 2147483647;
How should I chop the 32 bit integer variable into 4 separate 8 bit std_logic_vectors as expected by my UART code, and how should I pass these to the UART one byte at a time ?
I am aware std_logic_vector(to_unsigned(Count, 32)) will convert the integer variable into a 32 bit std_logic_vector, but then what ? Should I create a 32 bit std_logic_vector, assign the converted Count value to it, then subdivide it using something like the following code ? I realise the following assumes the count variable does not change during the 4 clock cycles, and assumes the UART can accept a new byte every clock cycle, and lacks any means of re-triggering the 4 byte transmit cycle, but am I on the right track here, or is there a better way ?
variable CountOut : std_logic_vector(31 downto 0);
process (clock)
variable Index : integer range 0 to 4 := 0;
begin
if rising_edge(clock) then
CountOut <= std_logic_vector(to_unsigned(Count, 32);
if (Index = 0) then
UartData(7 downto 0) <= CountOut(31 downto 24);
Index := 1;
elsif (Index = 1) then
UartData(7 downto 0) <= CountOut(23 downto 16);
Index := 2;
elsif (Index = 2) then
UartData(7 downto 0) <= CountOut(15 downto 8);
Index := 3;
elsif (Index =31) then
UartData(7 downto 0) <= CountOut(7 downto 0);
Index := 4;
else
Index := Index;
end if;
end if;
end process;
Any comments or recommendations would be appreciated.
Thanks,
MAI-AU.
You seem to be on the right track. I believe there are two basic solutions to this problem:
Register the output value as a 32-bit vector, and use different ranges for each output operation (as you did in your code example)
Register the output value as a 32-bit vector, and shift this value 8 bits at a time after each output operation. This way you can use the same range in all operations. The code below should give you an idea:
process (clock)
variable Index: integer range 0 to 4 := 0;
begin
if rising_edge(clock) then
if (Index = 0) then
CountOut <= std_logic_vector(to_unsigned(Count, 32));
Index := Index + 1;
elsif (Index < 4) then
UartData <= CountOut(31 downto 24);
CountOut <= CountOut sll 8;
Index := Index + 1;
end if;
end if;
end process;
Also, please check your assignments, in your example CountOut is declared as a variable but is assigned to as a signal.
There's nothing wrong with the code you've shown. You can do something to separate the the assignment to UartData using Index to allow a loop.
library ieee;
use ieee.std_logic_1164.all;
entity union is
end entity;
architecture foo of union is
type union32 is array (integer range 1 to 4) of std_logic_vector(7 downto 0);
signal UartData: std_logic_vector(7 downto 0);
begin
TEST:
process
variable quad: union32;
constant fourbytes: std_logic_vector(31 downto 0) := X"deadbeef";
begin
quad := union32'(fourbytes(31 downto 24), fourbytes(23 downto 16),
fourbytes(15 downto 8),fourbytes(7 downto 0));
for i in union32'RANGE loop
wait for 9.6 us;
UartData <= Quad(i);
end loop;
wait for 9.6 us; -- to display the last byte
wait; -- one ping only
end process;
end architecture;
Or use a type conversion function to hide complexity:
library ieee;
use ieee.std_logic_1164.all;
entity union is
type union32 is array (integer range 1 to 4) of std_logic_vector(7 downto 0);
end entity;
architecture fee of union is
signal UartData: std_logic_vector(7 downto 0);
function toquad (inp: std_logic_vector(31 downto 0)) return union32 is
begin
return union32'(inp(31 downto 24), inp(23 downto 16),
inp(15 downto 8), inp( 7 downto 0));
end function;
begin
TEST:
process
variable quad: union32;
constant fourbytes: std_logic_vector(31 downto 0) := X"deadbeef";
begin
quad := toquad (fourbytes);
for i in union32'RANGE loop
wait for 9.6 us;
UartData <= Quad(i);
end loop;
wait for 9.6 us; -- to display the last byte
wait; -- one ping only
end process;
end architecture;
And gives the same answer.
I am new to vhdl programming. I recently got a task to change value of std_logic_vector in a shift register sensitive to clock signal by pressing a button.
When I'm holding KEY(2) the value of shift register changes but it's not shifting unless I release the button. Is it possible to modify my code below so it would be sensitive to rising edge of KEY(2)? Or is there any other possibility to change a value of the vector by pressing the KEY(2) button and it would be shifting even if I'm holding the button?
Thank you for your answer. I would be really grateful and it would really help me a lot.
Sorry for my bad English. Have a nice time.
ENTITY hadvhdl IS PORT (
CLOCK_50 : IN STD_LOGIC;
KEY : IN STD_LOGIC_VECTOR (3 downto 0);
LEDR : OUT STD_LOGIC_VECTOR (15 downto 0)
);
END hadvhdl;
ARCHITECTURE rtl OF hadvhdl IS
shared variable register : std_logic_vector(15 downto 0) := (1 downto 0=>'1', others=>'0');
shared variable count : integer range 1 to 4 :=1;
BEGIN
changecount: process (KEY)
begin
if rising_edge(KEY(2)) then
if count<4 then
count := count + 1;
else
count := 1;
end if;
end if;
end process;
shift: process (CLOCK_50, KEY)
variable up : BOOLEAN := FALSE;
variable reg : std_logic_vector(15 downto 0) := (1 downto 0=>'1', others=>'0');
begin
if rising_edge(CLOCK_50) then
if (KEY(2)='1') then
case count is
when 1 => register := (1 downto 0=>'1', others=>'0');
when 2 => register := (2 downto 0=>'1', others=>'0');
when 3 => register := (3 downto 0=>'1', others=>'0');
when 4 => register := (4 downto 0=>'1', others=>'0');
end case;
end if;
reg := register;
LEDR <= reg;
if up then
reg := reg(0) & reg(15 downto 1);
else
reg := reg(14 downto 0) & reg(15);
end if;
register := reg;
end if;
end process;
END rtl;
Don't use variables! (at least as VHDL-beginner)
Don't use push buttons as clocks (e.g. in rising_edge)
Use only one clock in your design (seem o.k. in your case)
Keep in mind that a mechanical push button do bounces.
And here is a variant for an edge detection:
-- in entity
clk ; in std_logic;
sig_in : in std_logic;
...
signal sig_old : std_logic;
signal sig_rise : std_logic;
signal sig_fall : std_logic;
...
process
begin
wait until rising_edge( clk);
-- defaults
sig_rise <= '0';
sig_fall <= '0';
-- shift value in
sig_old <= sig_in;
-- do some real action
if sig_old = '0' and sig_in = '1' then
sig_rise <= '1';
end if;
if sig_old = '1' and sig_in = '0' then
sig_fall <= '1';
end if;
end process;