VHDL clock divider for controlling duty and phase - vhdl

Question

I am using a high speed clock (from an internal PLL) and attempting to divide it down to generate 2 clocks with varying duty and phase relationships. The code operates correctly if I single-step the input clock. As the frequency increases, the phase and duty of the secondary output (iDM_out in the code sample) gets corrupted. At some frequencies, the duty cycle of the secondary output will be correct. At other frequencies, the duty cycle might go to 90 or 199%. Ditto with the phase relationship (DMDelay). I've seem some articles about the need for clock buffers so I've trying a few types BUFF, CLKBUF and CLKINT on the output and it seems to make it worse. Does anybody have any ideas about what might be causing this condition?
use work.A208_pckgs.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DutyPhaseMod is
port (
rst : in std_logic;
GLA : in std_logic; -- GLA is 36x faster than target frequency
EXDuty : in std_logic_vector(4 downto 0); -- the number of GLA clock cycles for the EX duty cycle
DMDuty : in std_logic_vector(4 downto 0); -- the number of GLA clock cycles for the DM duty cycle
DMDelay : in std_logic_vector(4 downto 0); -- the number of GLA clock cycles for the DM phase delay
EX_out : out std_logic;
DM_out : out std_logic
);
end entity;
architecture behavioral of DutyPhaseMod is
signal iGLA : std_logic;
signal iFREQlen : integer range 0 to 35;
begin
process (rst, GLA)
variable iEX_out : std_logic;
variable iDM_out : std_logic;
variable iEXctr : natural range 0 to 35;
variable iDMctr : natural range 0 to 35;
begin
iFREQlen <= 35; -- number of clock cycles
if rst = '1' then -- reset the counters on reset signal
iEXctr := 0;
iDMctr := 0;
elsif rising_edge(GLA) then
if iEXctr <= unsigned(EXDuty) then -- first part of EX the duty cycle
iEX_out := '1';
iEXctr := iEXctr + 1;
elsif iEXctr < iFREQlen then -- second part of EX duty cycle
iEX_out := '0';
iEXctr := iEXctr + 1;
else -- set for the start of the next cycle
iEX_out := '1';
iEXctr := 0;
end if;
if iEXctr = unsigned(DMDelay) then -- reset for DM phase offset
iDMctr := 0;
elsif iDMctr <= unsigned(DMDuty) then -- first part of the DM duty cycle
iDM_out := '1';
iDMctr := iDMctr + 1;
elsif iDMctr <= iFREQlen - 1 then -- second part of the DM duty cycle
iDM_out := '0';
iDMctr := iDMctr + 1;
else -- set for the start of the next cycle
iDM_out := '1';
end if;
EX_out <= iEX_out;
DM_out <= iDM_out;
end if;
end process;
end behavioral;

Answer 1

I'm going to go out on a limb and answer my own question. Feel free to comment if you feel that my answer is not correct (or you can add/clarify further.) I decided to split my entity into two processes and it seems to work properly. The first process handles the base clock division on the rising_edge of the high speed clock. The second process handles the secondary (phase delayed) clock on the falling_edge of the high speed clock.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DutyPhaseMod is
port (
rst : in std_logic;
GLA : in std_logic;
EXDuty : in std_logic_vector(3 downto 0);
DMDuty : in std_logic_vector(3 downto 0);
DMDelay : in std_logic_vector(4 downto 0);
EX_out : out std_logic;
DM_out : out std_logic
);
end entity;
architecture behavioral of DutyPhaseMod is
signal iGLA : std_logic;
signal iFREQlen : integer range 0 to 35;
signal iEXctr : natural range 0 to 35;
begin
process (rst, GLA)
variable iEX_out : std_logic;
begin
iFREQlen <= 35;
if rst = '1' then
iEXctr <= 0;
elsif rising_edge(GLA) then
if iEXctr <= unsigned(EXDuty) then
iEX_out := '1'; --
iEXctr <= iEXctr + 1;
elsif iEXctr < iFREQlen then
iEX_out := '0';
iEXctr <= iEXctr + 1;
else
iEX_out := '1';
iEXctr <= 0;
end if;
EX_out <= iEX_out;
end if;
end process;
process (rst, GLA)
variable iDM_out : std_logic;
variable iDMctr : natural range 0 to 30;
begin
case FW_FREQ is
when F_46 =>
iFREQlen <= 35;
when F_82 =>
iFREQlen <= 23;
end case;
if rst = '1' then
iDMctr := 0;
elsif falling_edge(GLA) then
if iEXctr = unsigned(DMDelay) then
iDMctr := 0;
elsif iDMctr <= unsigned(DMDuty) then
iDM_out := '1';
iDMctr := iDMctr + 1;
elsif iDMctr <= iFREQlen - 1 then
iDM_out := '0';
iDMctr := iDMctr + 1;
else
iDM_out := '1';
end if;
DM_out <= iDM_out;
end if;
end process;
end behavioral;