When I preprocess a C++ file like this:
g++ -E source.cpp
the preprocessed file still contains a lot of preprocessor instructions like these:
# 1 "/usr/include/features.h" 1 3 4
# 367 "/usr/include/features.h" 3 4
# 1 "/usr/include/x86_64-linux-gnu/sys/cdefs.h" 1 3 4
I don't need them. How can I get a preprocessed file without these instructions?
You can use the -P option. It prevents GCC from creating these line options:
g++ -E -P source.cpp
Related
In my make file I have 2 parameters defined as below with default values.
PARAM1 ?= 2
PARAM2 ?= 11
I am using these parameters in my target cpp_run.
cpp_run:
./dig_vr_App $(PARAM1) $(PARAM2) |& tee run_Cpp.log
However if I pass the parameters from the command line for example
make cpp_run PARAM1=102 PARAM2=0
the make file still picks up the default values, i.e., 2 and 11 (from the log file run_cpp.log). I followed other posts which says use PARAM1=num1 and PARAM2=num2 in the command line as shown above but it doesn't work.
As I said in my comments, you are not telling us something. I created this test:
$ cat Makefile
PARAM1 ?= 2
PARAM2 ?= 11
cpp_run:
#echo ./dig_vr_App $(PARAM1) $(PARAM2)
and it works exactly how I'd expect:
$ make --version | head -n2
GNU Make 4.3
Built for x86_64-pc-linux-gnu
$ make cpp_run
./dig_vr_App 2 11
$ make cpp_run PARAM1=102 PARAM2=0
./dig_vr_App 102 0
So there's something about your environment or makefile that you haven't explained to us.
I am trying to preprocess a .h file and produce a new .h file with all of the # preproc directives resolved. I used gcc -E file.c command and I always get this output:
# 1 "file.c"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "file.c"
Which command should I use to produce a new preprocessed .h file?
From https://gcc.gnu.org/onlinedocs/gcc/Preprocessor-Options.html
-P
Inhibit generation of linemarkers in the output from the preprocessor. This might be useful when running the preprocessor on something that is not C code, and will be sent to a program which might be confused by the linemarkers.
Simply use
gcc -E -P file.c
How i could save le preprocessor in output file with specific name as x or y ?
I tried the command line :
gcc -E -o pgcd.c x.o
But it don't seem being the solution.
ps: the file doesn't exist before the compilation, i just would save the preprocessor in a file with the name i defined.
Thank you for any help.
gcc -E file.c
will preprocess file.c and write the preprocessed source code to the
standard output (console). So to save the preprocessed output, redirect
the standard output to a file of your choice:
gcc -E file.c > somefile
It is a bad idea for somefile to have an .o extension. GCC and other
tools interpret the .o extension as meaning that the file contains object
code, as output by compilation. Preprocessing file.c does not produce
object code. It just produces preprocessed source code, which you might later compile.
The conventional file extension for preprocessed C source code is .i
(.ii for preprocessed C++ source code). Therefore
gcc -E file.c > file.i
is the appropriate choice.
You will discover that file.i contains preprocessor line-markers, e.g.
# 1 "file.c"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "/usr/include/stdc-predef.h" 1 3 4
# 1 "<command-line>" 2
# 1 "file.c"
# 1 "/usr/include/stdio.h" 1 3 4
# 27 "/usr/include/stdio.h" 3 4
...
...
If you don't want these line-markers to appear in the output, add the -P
option:
gcc -E -P file.c > file.i
The GCC -save-temps flag can also be used to save the processed file in *.i files (although this differs from -E in that compilation of the files are not halted after the pre-processor stage).
Is it possible to achive something like this with gcc -E?
src.c:
z
#define FOO bar
z
actual preprocess result:
# 1 "src.c"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "src.c"
z
z
desired preprocess result:
# 1 "src.c"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "src.c"
z
/* #define FOO bar */
z
It can't be done directly, but if you really wanted this, you could pass the -dD option to cpp (via the gcc driver it might look like -Wp,-dD; then further process the output to turn the #defines into comments.
-dD tells the preprocessor to keep the #define directives in the resulting output.
If you want to keep the defines as comments maybe you can study MCPP manual, I sort of remember there is an option for this.
At least -C preserves the comments, and -K is described as "embed macro annotation into comments".
https://linux.die.net/man/1/mcpp
What does "macro annotations embedding in comments" mean in mcpp?
If that doesn't work you'll have to make a parser. either use clang as a library and iterate on preprocessor tokens. Or do your own with AntlR (there are many ready to use C grammars)
How can I use gcc to expand macros in files containing (for example) python/php/perl code?
Having a file containing:
#define foo very important stuff
#define feast Christmas
I should take care of some foo for feast.
I have tried to use:
$ gcc -x c++ -E - < text.txt > output.txt
but it displays this:
$ cat output.txt
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "<stdin>"
I should take care of some very important stuff for Christmas.
How to avoid gcc to add those comments and (if possible) the extra newlines?
You should be aware of this warning from the online docs for the GNU C preprocessor
The C preprocessor is intended to be
used only with C, C++, and Objective-C
source code. In the past, it has been
abused as a general text processor. It
will choke on input which does not
obey C's lexical rules. For example,
apostrophes will be interpreted as the
beginning of character constants, and
cause errors. Also, you cannot rely on
it preserving characteristics of the
input which are not significant to
C-family languages. If a Makefile is
preprocessed, all the hard tabs will
be removed, and the Makefile will not
work.
The '#' lines in the output could be the least of your problems.
You might do better with a different tool, such as m4.
I do not know if there is a specific option for gcc.
You can postprocess with a grep
$ gcc -x c++ -E - < text.txt | grep -v '^#' > output.txt