MachX03 library error in Active-hdl for fpga simulation - vhdl

Question

edit: I just reinstalled lattice diamond and the updates, Active-hdl was installed automatically, but the simulation still gives me the same error. when i change library machXO3; use machXO3.all; to library machXO2; use machXO2.all; it compiles..
I'm trying to write a test bench for a simple implementation of OSCH, but I am not being able to get the testbench to work.
I managed to get it to work a few months ago but I lost the file I was working on.
this is the vhdl code I have:
library ieee;
use ieee.std_logic_1164.all;
-- For Main Clock --
library machXO3;
use machXO3.all;
--------------------
entity Clock is
port (stdby : in std_logic;
osc_int: out std_logic
);
end Clock;
architecture Clock_behav of Clock is
COMPONENT OSCH
-- synthesis translate_off
GENERIC (NOM_FREQ: string := "2.56");
-- synthesis translate_on
PORT (STDBY : IN std_logic;
OSC : OUT std_logic
);
END COMPONENT;
begin
Clock: OSCH
-- synthesis translate_off
GENERIC MAP( NOM_FREQ => "2.56" )
-- synthesis translate_on
PORT MAP ( STDBY => stdby,
OSC => osc_int
);
end Clock_behav;
This is the testbench, most of it was generated by lattice-diamond I only added stdby <= '0';
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT Clock
PORT(
stdby : IN std_logic;
osc_int : OUT std_logic
);
END COMPONENT;
SIGNAL stdby : std_logic;
SIGNAL osc_int : std_logic;
BEGIN
-- Please check and add your generic clause manually
uut: Clock PORT MAP(
stdby => stdby,
osc_int => osc_int
);
stdby <= '0';
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
--wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
Lattice-diamond is telling me that everything is okay, but when I run everything in Active-hdl, to simulate, I get these errors:
# Error: COMP96_0059: Main.vhd : (5, 1): Library "machXO3" not found.
# Error: COMP96_0078: Main.vhd : (6, 5): Unknown identifier "machXO3".
# Compile Architecture "Clock_behav" of Entity "Clock"
# Error: COMP96_0056: Main.vhd : (15, 1): Cannot find referenced entity declaration "Clock".
# Compile failure 3 Errors 0 Warnings Analysis time : 16.0 [ms]

Answer 1

Looking at C:\lscc\diamond\3.10_x64\active-hdl\vlib\, there seems to be no machXO3 library, but there is a machxo, machxo2 and a machxo3l library. changing library machXO3; use machXO3.all; to library machXO3l; use machXO3l.all; to making some small modifications to the test bench, everything seems to work out fine.
new testbench
-- VHDL Test Bench Created from source file Clock.vhd -- Fri Feb 22 13:56:19 2019
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispLEVER Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the
-- stimulus for your design.
-- 3) VHDL simulations will produce errors if there are Lattice FPGA library
-- elements in your design that require the instantiation of GSR, PUR, and
-- TSALL and they are not present in the testbench. For more information see
-- the How To section of online help.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT Clock
PORT(
stdby : IN std_logic;
osc_int : OUT std_logic
);
END COMPONENT;
SIGNAL stdby : std_logic;
SIGNAL osc_int : std_logic;
constant PERIOD : time := 20 ns;
BEGIN
-- Please check and add your generic clause manually
uut: Clock PORT MAP(
stdby => stdby,
osc_int => osc_int
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
stdby <= '0';
wait for PERIOD ;
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;