How to fix 'ERROR:Xst - basic_stringFATAL_ERROR' error in Xilinx fpga? - vhdl

Question

I have been trying to synthesize a vhdl code which simulates perfectly in Active HDL but I get the following error when synthesizing.
ERROR:Xst - basic_stringFATAL_ERROR:Xst:Portability/export/Port_Main.h:159:1.18 - This application has discovered an exceptional condition from which it cannot recover. For technical support on this issue, please visit http://www.xilinx.com/support.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
--use IEEE.NUMERIC_STD_UNSIGNED.all;
library work;
use work.common.all;
library UNISIM;
use UNISIM.VComponents.all;
entity main is
port(
CLK : in STD_LOGIC;
reset : in STD_LOGIC;
V_Out : out STD_LOGIC
);
end main;
--}} End of automatically maintained section
architecture main of main is
signal text : string (1 to 15) := "This is a Test.";
signal text_len : integer := 15;
signal x : integer := 50;
signal y : integer := 50;
type vramt is array (0 to H_480_272p_AV*V_480_272p_AV-1) of std_logic_vector (0 downto 0);
signal vram : vramt := (others => (others => '0'));
--signal vram : std_logic_vector(H_480_272p_AV*V_480_272p_AV-1 downto 0) := (others => '0');
attribute RAM_STYLE : string;
attribute RAM_STYLE of vram: signal is "BLOCK";
signal vram_we : std_logic;
signal vram_addr, vram_wraddr : INTEGER range 0 to H_480_272p_AV*V_480_272p_AV-1;
signal rom_addr : std_logic_vector(10 downto 0);
signal rom_data : std_logic_vector(7 downto 0);
begin
inst_get_char : entity work.Font_Rom PORT MAP (
clk => CLK,
addr => rom_addr,
data => rom_data
);
Process (CLK)
begin
if rising_edge (CLK) then
if vram_addr = H_480_272p_AV*V_480_272p_AV-1 then
vram_addr <= 0;
end if;
vram_addr <= vram_addr + 1;
V_Out <= vram(vram_addr)(0);
end if;
end process;
Process (CLK)
variable char_count : integer := 1;
variable pix_line : integer := 0;
variable bit_count : integer := 0;
variable curr_char : std_logic_vector(7 downto 0);
variable bit_data : std_logic;
begin
if rising_edge(CLK) then
if bit_count = 0 then
rom_addr <= std_logic_vector(to_unsigned(character'pos(text(char_count)), 7)) & std_logic_vector(to_unsigned(pix_line, 4));
end if;
bit_data := rom_data(bit_count);
vram_wraddr <= (y + pix_line)*H_480_272p_AV + (x + bit_count + (8* (char_count-1)));
vram(vram_wraddr)(0) <= bit_data;
if bit_count = 7 then
bit_count := 0;
if pix_line = 15 then
pix_line := 0;
if char_count = text_len then
char_count := 1;
else
char_count := char_count + 1;
end if;
else
pix_line := pix_line + 1;
end if;
else
bit_count := bit_count + 1;
end if;
end if;
end Process;
end main;