I am somewhat new to VHDL and am trying to create a simple code for a Flip Flop D. My code compiles correctly, however when I run my Testbench tb_FlipFlopD in ModelSim Altera, the program opens but there's no wave, and I don't have the option to add it either.
The bug is problaby in my Testbench.
My Top-level identity code FlipFlopD:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FlipFlopD is
port( clock: in std_logic;
D: in std_logic;
Q: out std_logic
);
end FlipFlopD;
architecture RTL of FlipFlopD is
begin
Q <= D when clock = '1' and clock'event;
end RTL;
My Testbench tb_FlipFlopD:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_FlipFlopD is
end tb_FlipFlopD;
architecture teste of tb_FlipFlopD is
component FlipFlopD is
port (
clock : in std_logic;
D : in std_logic;
Q : out std_logic
);
end component;
signal I: std_logic;
signal O: std_logic;
signal C: std_logic := '0';
constant clk_period : time := 1 ns;
begin
instancia_FlipFlopD: FlipFlopD port map( D => I, Q => O, clock => C);
I <= '0', '1' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns;
clk_process : process
begin
C <= '0';
wait for clk_period/2;
C <= '1';
wait for clk_period/2;
end process;
end teste;
Your problem is that you simulation runs, but never stops; it just keeps on running forever.
Any VHDL (or Verilog) simulation will keep running if there is still stuff to do. This process:
clk_process : process
begin
C <= '0';
wait for clk_period/2;
C <= '1';
wait for clk_period/2;
end process;
generates an event (a change) on the the signal C every clk_period/2. Forever. To cure this, you need to put something in to stop this, eg:
clk_process : process
begin
while not STOP loop
C <= '0';
wait for clk_period/2;
C <= '1';
wait for clk_period/2;
end loop;
wait;
end process;
The wait; at the end of the process, waits forever. Signal STOP is a boolean:
signal STOP : boolean := false;
Then you need something like this to drive signal STOP:
STOP <= false, true after 10 ns;
Related
My code will not simulate an output when running the VWF file.
I have tried changing the code several different time and don't really understand what I'm doing wrong.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_JM is
Port (
up_down : in std_logic;
LED : out std_logic;
Q : Buffer integer Range 0 to 7);
end Counter_JM;
architecture archi of Counter_JM is
Begin
-- up/down counter
process (up_down)
begin
if (Q=7) then
Q<=0;
end if;
if (up_down = '1') then
Q <= Q + 1;
else
Q<=0;
end if;
if (Q=0 or Q=1) then
LED <= '0';
else
LED <= '1';
end if;
end process;
end archi;
The LED output should show high for 4 cycles and low for 2 on the VWF file
I don't know why you use up_down. But as Oldfart said, you don't have a clock. I have simplified and modified your code (it works for me (in modelsim):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_JM is
Port (
clk: in std_logic;
up_down : in std_logic;
LED : out std_logic
);
end Counter_JM;
architecture archi of Counter_JM is
Begin
process (clk)
variable Q: integer range 0 to 7;
begin
if rising_edge(clk) then
-- up/down counter
Q := Q + 1;
if Q=1 or Q=2 then
LED <= '0';
else
LED <= '1';
end if;
if Q = 7 then
Q := 0;
end if;
end if;
end process;
end archi;
and also created/generated a simple testbench here :
`-- Testbench automatically generated online
-- at http://vhdl.lapinoo.net
-- Generation date : 7.6.2019 11:22:53 GMT
library ieee;
use ieee.std_logic_1164.all;
entity tb_Counter_JM is
end tb_Counter_JM;
architecture tb of tb_Counter_JM is
component Counter_JM
port (clk : in std_logic;
up_down : in std_logic;
LED : out std_logic);
end component;
signal clk : std_logic;
signal up_down : std_logic;
signal LED : std_logic;
constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
begin
dut : Counter_JM
port map (clk => clk,
up_down => up_down,
LED => LED);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
-- EDIT: Check that clk is really your main clock signal
clk <= TbClock;
stimuli : process
begin
-- EDIT Adapt initialization as needed
up_down <= '0';
-- EDIT Add stimuli here
wait for 100 * TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
wait;
end process;
end tb;
-- Configuration block below is required by some simulators. Usually no need to edit.
configuration cfg_tb_Counter_JM of tb_Counter_JM is
for tb
end for;
end cfg_tb_Counter_JM;`
I have written a simple entity in VHDL to blink an LED and am trying to simulate it in ModelSim but am getting no transitions on the output.
Here is my HDL file for the LED_Blink entity:
Library IEEE;
use IEEE.Std_logic_1164.all;
entity LED_Blink is
generic (
g_SYSTEM_CLOCK_PERIOD : in time := 10 ns; -- 100 MHz clock period
g_LED_ON_TIME : in time := 1 sec
);
port(
system_clock : in Std_logic;
reset_fpga_L : in Std_logic;
led_out : out Std_logic
);
end entity LED_Blink;
architecture RTL of LED_Blink is
signal led_state : Std_logic;
constant COUNTER_RELOAD_VAL : natural := g_LED_ON_TIME/g_SYSTEM_CLOCK_PERIOD;
begin
process(reset_fpga_L, system_clock)
variable counter : natural range 0 to COUNTER_RELOAD_VAL := COUNTER_RELOAD_VAL;
begin
if reset_fpga_L = '0' then
counter := COUNTER_RELOAD_VAL;
led_state <= '0';
elsif rising_edge(system_clock) then
if counter = 0 then
led_state <= not led_state;
counter := COUNTER_RELOAD_VAL;
else
counter := counter - 1;
end if;
end if;
led_out <= led_state;
end process;
end architecture RTL;
And here is my test-bench:
Library IEEE;
use IEEE.Std_logic_1164.all;
entity LED_Blink_TB is
end entity LED_Blink_TB;
architecture RTL of LED_Blink_TB is
signal reset_fpga_L : Std_logic := '0';
signal system_clock : Std_logic := '0';
signal led_out : Std_logic := '0';
begin
G1: entity work.LED_Blink(RTL) port map(reset_fpga_L, system_clock, led_out);
CLK: process
begin
while now <= 5 sec loop
system_clock <= not system_clock;
wait for 5 ns;
end loop;
wait;
end process CLK;
STIM: process
begin
reset_fpga_L <= '0';
wait for 100 ns;
reset_fpga_L <= '1';
wait for 4 sec;
reset_fpga_L <= '0';
wait for 50 ns;
reset_fpga_L <= '1';
wait;
end process STIM;
end architecture RTL;
I can't figure out why I'm not seeing any transitions on led_out when I run my test-bench in the simulator. I've taken care to add the waves for system_clock, reset_fpga_L, and led_out to the trace view. Do you see anything in my code that might be an issue? Thanks for your help.
A second form of the testbench can be used make generation of inputs to LED_Blink depend on the values supplied as generics:
library ieee;
use ieee.std_logic_1164.all;
entity led_blink_tb is
end entity;
architecture foo of led_blink_tb is
constant CLK_PERIOD: time := 100 ms;
constant LED_ON: time := 500 ms;
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal led: std_logic;
begin
DUT:
entity work.led_blink
generic map ( CLK_PERIOD, LED_ON)
port map (
system_clock => clk,
reset_fpga_l => reset_n,
led_out => led
);
CLOCK:
process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
if now > 2.5 sec then
wait;
end if;
end process;
STIMULI:
process
begin
reset_n <= '0';
wait for CLK_PERIOD * 2;
reset_n <= '1';
wait;
end process;
end architecture;
The idea, both the testbench and the model depend on constants supplied as generics making changing the parameters require less work.
Also note the association list in the port map uses named association.
If we take a look at the original testbench port map:
G1: entity work.LED_Blink(RTL) port map(reset_fpga_L, system_clock, led_out);
We see that the first positional association to the formal system_clock is associated with the actual reset_fpga_L while the second positional association representing formal reset_fpga_L is associated with the actual system_clock.
The two actual associations are in reversed order.
this is the VHDL code for synchronous type counter. As I'm still new in vhdl, I'm having problem in writing the testbench to simulate this code. can anyone give me some suggestions on how to write the testbench? thank you
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cnt4 is
port( CLK, RST : in std_logic;
Q : out std_logic);
end cnt4;
architecture EX1 of cnt4 is
signal cnt : std_logic_vector(1 downto 0);
begin
process(CLK, RST)
begin
if RST = '1' then
cnt <= "00";
elsif CLK'event and CLK = '1' then
if cnt = 3 then
cnt <= "00";
Q <= '1';
else
cnt <= cnt + 1;
Q <= '0';
end if;
end if;
end process;
end EX1;
this is the testbench that i've tried to write so far
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TESTBENCH is
end TESTBENCH;
architecture EX1 of TESTBENCH is
signal CLK, RST : std_logic;
signal Q : std_logic;
component cnt4
port( CLK, RST : in std_logic;
Q : out std_logic );
end component;
begin
U0: cnt4 port map(CLK, RST, Q);
process
begin
CLK <= '1';
wait for 10 ns;
CLK <= '0';
wait for 10 ns;
wait;
end process;
process
begin
RST <= '0'; wait for 10 ns;
RST <= '1'; wait for 10 ns;
wait;
end process;
end EX1;
the simulation result using the testbench above is as in the picture
simulation
it may look ridiculous as I don't really know how to write the testbench. would be glad if anyone can help me
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_flip_flop is
port (
D : in STD_LOGIC;
Q : inout STD_LOGIC;
Q_tonos : out STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC
);
end D_flip_flop;
architecture Behavioral of D_flip_flop is
begin
process_flip_flip: process
begin
wait until CLK'EVENT AND CLK = '1';
if(RST='1') then
Q <= '0';
else
Q <= D;
end if;
Q_tonos <= not Q;
end process process_flip_flip;
end Behavioral;
-------------------------
--testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_flip_flop IS
END test_flip_flop;
ARCHITECTURE tb OF test_flip_flop IS
COMPONENT D_flip_flop
PORT(
D : IN std_logic;
Q : INout std_logic;
Q_tonos : OUT std_logic;
CLK : IN std_logic;
RST : IN std_logic
);
END COMPONENT;
signal D : std_logic ;
signal CLK : std_logic ;
signal RST : std_logic ;
signal Q : std_logic;
signal Q_tonos : std_logic;
constant CLK_period : time := 10 ns;
signal stopClk : boolean;
BEGIN
-- Instantiate the Unit Under Test (UUT)
dut: D_flip_flop PORT MAP (
D => D,
Q => Q,
Q_tonos => Q_tonos,
CLK => CLK,
RST => RST
);
CLK_process :process
begin
while not stopClk loop
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end loop;
wait;
end process CLK_process;
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
D <= '0';
RST <= '1';
wait for 100 ns;
D <= '0';
RST <= '0';
wait for 100 ns;
D <= '1';
RST <= '0';
wait for 100 ns;
D <= '1';
RST <= '0';
wait for 100 ns;
wait;
end process;
END;
You are missing one line in your testbench, I think:
D <= '1';
RST <= '0';
wait for 100 ns;
stopClk <= TRUE; -- add this line
wait;
end process;
END;
http://www.edaplayground.com/x/56Mm
That way, when the test is finished, the clock stopClk signal turns off the clock generator and the simulation finishes. It finishes because it reaches a state called event starvation. Every time a line of code containing a signal assignment is executed, an event is added to the simulators event queue (its "to do list"). If you create a situation where no such lines continue to be executed, then the event queue becomes empty. This is event starvation. The simulator detects that and the simulation stops. (If you think about, what else could it do?)
Without this extra line, the simulation runs forever, because the clock generation process executes signal assignments forever, so the event queue is never empty.
Not really an answer, but: consider using if rising_edge(CLK) or maybe if CLK='1' and CLK'event instead of wait until. Not all synhtesis tools support that kind of code and anyway it's rare to see it in professional world ;)
p.s. stopClk signal is not driven (or was it?) Your TB clock is enably by that, yet I guess it remains 'u' for the whole simulation. Unless forced in the simulation.
I'm having some trouble implementing a ring oscillator. I don't care about it working on an FPGA. I only want to simulate using Xilinx ISE. Is the code below acceptable? I also addded the test bench. Thanks!
Code
library ieee;
use ieee.std_logic_1164.all;
-- 5 Ring Oscillator
entity ring_osc is
port (ro_en : in std_logic;
delay : in time;
ro_out : out std_logic);
end ring_osc;
architecture behavioral of ring_osc is
signal gate_out : std_logic_vector(5 downto 0) := (others => '0');
begin
process
begin
gate_out(0) <= ro_en and gate_out(5);
wait for delay;
gate_out(1) <= not(gate_out(0));
wait for delay;
gate_out(2) <= not(gate_out(1));
wait for delay;
gate_out(3) <= not(gate_out(2));
wait for delay;
gate_out(4) <= not(gate_out(3));
wait for delay;
gate_out(5) <= not(gate_out(4));
wait for delay;
ro_out <= gate_out(5);
end process;
end behavioral;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
entity ring_osc_tb is
end ring_osc_tb;
architecture behavior of ring_osc_tb is
-- component declaration for the unit under test (uut)
component ring_osc
port (ro_en : in std_logic;
delay : in time;
ro_out : out std_logic);
end component;
-- Inputs
signal ro_en : std_logic := '0';
signal delay : time := 0.5 ns;
-- Outputs
signal ro_out : std_logic;
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
begin
-- instantiate the unit under test (uut)
uut: ring_osc port map (
ro_en => ro_en,
delay => delay,
ro_out => ro_out
);
-- clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- stimulus process
stim_proc: process
begin
ro_en <= '1';
delay <= 0.5 ns;
wait for 10*clk_period;
delay <= 1 ns;
wait for 5*clk_period;
assert false report "End of Simulation" severity failure;
end process;
end;
The process with sequential wait does not describe the concurrent nature of the gates in the Ring oscillator, since execution is suspended for delay time at each wait, which is not the way a real word design operates.
A description with concurrent evaluation of all the gates can be:
gate_out(0) <= ro_en and gate_out(5) after delay;
inv_g : for i in 1 to gate_out'high generate
gate_out(i) <= not gate_out(i - 1) after delay;
end generate;
ro_out <= gate_out(5);
This is for simulation only, as also noted in the question, due to the inherent loop nature of a ring oscillator.
Using test bench, with added disable at start:
-- Disable at start
ro_en <= '0';
delay <= 0.5 ns;
wait for 10 * 0.5 ns;
Then the resulting waveform is: