I have a program MAX + plus II version 10.2 07/10/2002. Found in the book program code VHDL - project. This project is called the "N-level processor." My program MAX + plus II version 10.2 throws out a library error: primary unit 'numeric_std' denoted by 'IEEE' must exist in library. The program code is given below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ste1_un is
port (clk : in std_logic;
pok : in integer range 0 to 255;
x : in unsigned (63 downto 0);
y : out unsigned (63 downto 0));
end ste1_un;
architecture ste1_un of ste1_un is
begin
process(clk)
variable poka : integer range 0 to 255;
variable res : unsigned (63 downto 0);
variable res1 : unsigned (63 downto 0) :=
X"0000000000000001";
begin
if clk'event and clk = '1' then
res1 :=x; -- X"0000000000000003";
poka := pok;
for i in 1 to poka loop
res := resize((res * res1), 64) ;
end loop;
y <= res;
res := X"0000000000000001";
end if;
end process;
end ste1_un;
I ask for help!
Related
I have a type declared in a package which I use in the port entity:
Package:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package ports_type is
constant N: positive := 3;
type t_ports_types is array(0 to N-1) of std_logic_vector (N-1 downto 0);
end package ports_type;
Module:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ports_type.all;
entity ports is
generic (
N : positive := 3
);
port(
inp : in t_ports_types;
outp : out std_logic_vector(N-1 downto 0)
);
end ports;
architecture Behavioral of ports is
begin
process(inp)
variable result : std_logic;
begin
for y in 0 to N-1 loop
result := '0';
for x in 0 to N-1 loop
result := result or inp(x)(y);
end loop;
outp(y) <= result;
end loop;
end process;
end Behavioral;
The problem is that I have to manually change the value of Nin the package, which is a problem if I want to instantiate the ports entity in another module, like:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ports_type.all;
entity ports_top is
generic (
N : positive := 3
);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
C : in std_logic_vector(N-1 downto 0);
Outp : out std_logic_vector(N-1 downto 0)
);
end ports_top;
architecture Behavioral of ports_top is
signal s_ports : t_ports_types;
begin
s_ports(0) <= A;
s_ports(1) <= B;
s_ports(2) <= C;
ports_0: entity work.ports(Behavioral)
generic map (
N => N
)
port map(
inp => s_ports,
outp => Outp
);
end Behavioral;
The goal would be to only change N in the top module and not in the package as well. Is that possible with vhdl'93?
Thanks for the help.
I have this code in my project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
entity sfixed_test is
port(x1 : in integer :=20;
x2 : in integer := 23;
N : out sfixed( 8 downto -8));
end sfixed_test;
architecture Behavioral of sfixed_test is
signal Ni,Nii,No,Noo,nb :integer;
signal Niii : sfixed(4 downto -20);
signal Nn : sfixed(4 downto -20);
signal N1max : integer := 34;
signal N1min : integer := 14;
signal N2max : integer := 56;
signal n2min : integer := 0;
begin
Ni <= x1-N1min;
Nii <= N1max-N1min;
Niii <= to_sfixed(Ni/Nii,Niii);
No <= x2-N2min;
Noo <= N2max-N2min;
Nn <= to_sfixed(No/Noo,Nn);
end Behavioral;
I want to convert result value from my division operation, but the value of Niii and Nn is zero went i try running my code in simulator. And te result of my project is not correct.
Please to helping me.
Thank you
I've got two 115bits unsigned vectors. I have to do some mod calculations on them, but Quartus shows those errors.
Error: In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Error: In lpm_divide megafunction, LPM_WIDTHD must be less than or equal to 64
Error: Can't elaborate inferred hierarchy "lpm_divide:Mod0"
I fully understand, that numbers are too large to perform mod. Is there a way/library/any idea how to solve this problem? I would love to avoid using any "substracting loop", and be as simple as possible. VHDL is not my world, and after academic project I will abandon it with pleasure :P
Application has to calculate modulo inversion. As far as I am not master from VHDL, I've tried doing it using fast powering + mod alghoritm. Application can sucks, it just has to work :d
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.altera_primitives_components.all;
entity inwersja is
port(
a: in unsigned(114 downto 0);
clk: in std_logic;
start: in std_logic;
reset: in std_logic;
c: out unsigned(114 downto 0);
ready: out std_logic);
end inwersja;
architecture i1 of inwersja is
begin
process(clk)
variable tempOutput : unsigned(114 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
variable temp : unsigned (114 downto 0):= a;
variable modul: unsigned(114 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101011";
variable power: unsigned(114 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001";
variable counter: integer := 0;
begin
if reset='1' then
tempOutput := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
ready <= '0';
elsif clk'event and clk='1' then
if start='0' then
ready<='0';
else
if (counter < 115) then
if (power(counter) /= '0') then
tempOutput := (tempOutput * temp) mod modul;
end if;
temp := (temp * temp) mod modul;
counter := counter + 1;
elsif (counter = 115) then
ready <= '1';
end if;
end if;
end if;
c <= tempOutput;
end process;
end i1;
In VHDL i want to add a number of 5 bits and a number of 8 bits.(Unsigned) And how many bits does the output have?
I want my code to answer the questions i just asked. My code currently look like this...
My code is:
library ieee;
use ieee-std_logic_1164.all;
entity adder is
port( a : in unsigned (7 downto 0);
b : in unsigned (4 downto 0); - - Need to convert this to 8 bit right? But how?
z : out unsigned(7 downto 0)); - - This one must be 8 bits right? Cuz a & b & z must have the same WL. Or am i wrong?
end adder;
archictecture add of adder is
begin
z <= a + b;
end archictecture;
In package numeric_std for function "+" (L, R: UNSIGNED) return UNSIGNED the length of the longest argument defines the return value length:
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end "+";
The maximum of the left and right arguments length is SIZE, the range of the two arguments is is resized to SIZE -1 downto 0 as arguments to ADD_UNSIGNED.
function ADD_UNSIGNED (L, R: UNSIGNED; C: STD_LOGIC) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
The RESULT's length is that of the L argument which is the same of both arguments to UNSIGNED_ADD. There is no carry out implied in the result.
As in your case the result, assigned to z can be 8 bits.
Fix the comment delimiters in the port declarations, add a use clause to access package numeric_std, fix a '-' that should be a '.', spelling of architecture and add a test bench adding values for a and b set to all '1's and you can analyze, elaborate and run your design without error, telling you there isn't an array length error executing.
To get that ninth 'bit' as an output of the adder you can RESIZE one of your arguments to + to 9 bits or concatenate one argument with leading zeros to make a 9 bit value:
z <= "0" & a + b;
It'll demonstrate that the 9th bit is needed for an accurate result:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
port(
a: in unsigned (7 downto 0);
b: in unsigned (4 downto 0);
z: out unsigned (8 downto 0)
);
end adder;
architecture add of adder is
begin
z <= "0" & a + b;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_adder is
end entity;
architecture foo of tb_adder is
signal a: unsigned (7 downto 0) := (others => '1');
signal b: unsigned (4 downto 0) := (others => '1');
signal z: unsigned (8 downto 0);
function unsigned_image(inp: unsigned) return string is
variable image_str: string (1 to inp'length);
alias input_str: unsigned (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
DUT:
entity work.adder
port map (
a => a,
b => b,
z => z
);
MONITOR:
process
begin
wait for 1 ns;
report "z = " & unsigned_image(z);
wait;
end process;
end architecture;
david_koontz#Macbook: ghdl -a adder.vhdl
david_koontz#Macbook: ghdl -e tb_adder
david_koontz#Macbook: ghdl -r tb_adder
adder.vhdl:54:9:#1ns:(report note): z = 100011110
Other than this correction:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Your code is fine.
Additionally, adding an 8 bit number and a 5 bit number produces a 9 bit number, because you can overflow. For example, "11111111" + "11111" overflows a 8 bit output, but doesn't overflow a 9 bit output.
I have a difficult question for "strong" solvers :
I am trying to synthesize the VHDL behavioral code which is shown at the end of this question.
When I used the line
m1Low := m1Low/m0Low;
the circuit was synthesizing and producing correct results. However, this was for a given input, fixed as constants in the code. When the input comes as signals from outside the circuit (here specifically the input hist which is an array of std_logic_vector), this does not synthesize anymore. I have to replace the / with a divide function:
m1Low := to_integer(divide(to_unsigned(m1Low,32),to_unsigned(m0Low,32)));
the circuit synthesizes for a huge amount of time. I left it overnight and it does not complete synthesis.
What do you suggest that I do?
Thank you
Haris
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.declarations.all;
entity behavioral_code is
generic ( NHIST : integer := 32 );
port (clk : in std_logic;
en : in std_logic;
hist : in vector_array;
thres : out std_logic_vector ( 31 downto 0) );
end behavioral_code;
architecture Behavioral of behavioral_code is
begin
process(en,clk)
type int_array is array (1 to NHIST) of integer;
variable m0Low : integer := 0;
variable m1Low : integer := 0;
variable m0High : integer := 0;
variable m1High : integer := 0;
variable varLow : integer := 0;
variable varHigh : integer := 0;
variable varWithin : integer := 0;
variable varWMin : integer := 900000000;
variable hist_var : int_array;
variable invertFlag: integer := 0;
variable nHistM1: integer := 0;
variable i: integer := 0;
variable j: integer := 0;
variable k: integer := 0;
variable l: integer := 0;
variable m: integer := 0;
variable n: integer := 0;
variable o: integer := 0;
variable p: integer := 0;
variable q: integer := 0;
variable temp: integer :=0;
variable thres_var: integer :=0;
begin
if(en = '1') then
for k in 1 to NHIST loop
hist_var(k) :=to_integer(unsigned(hist(k-1)));
end loop;
--for k in 1 to NHIST loop --COMMENT: OLD FIXED INPUT
-- hist_var(k) :=k;
--end loop;
nHistM1 := NHIST-1;
for i in 1 to nHistM1 loop
m0Low :=0;
m1Low :=0;
m0High :=0;
m1High :=0;
varLow :=0;
varHigh :=0;
for j in 1 to i loop
m0Low := m0Low + hist_var(j);
m1Low := m1Low + (j-1) * hist_var(j);
end loop;
if m0Low = 0 then
m1Low := i;
else
--m1Low := m1Low/m0Low;
m1Low := to_integer(divide(to_unsigned(m1Low,32),to_unsigned(m0Low,32)));
end if;
for m in i + 1 to NHIST loop
m0High := m0High + hist_var(m);
m1High := m1High + (m-1) * hist_var(m);
end loop;
if m0High = 0 then
m1High := i;
else
--m1High := m1High /m0High;
m1High :=to_integer(divide(to_unsigned(m1High,32),to_unsigned(m0High,32)));
end if;
for n in 1 to i loop
varLow := varLow + (n - 1- m1Low) * (n -1- m1Low) * hist_var(n);
end loop;
for o in i+1 to NHIST loop
varHigh := varHigh +(o -1- m1High) * (o -1- m1High) * hist_var(o);
end loop;
varWithin := m0Low * varLow + m0High * varHigh;
if varWithin < varWMin then
varWMin := varWithin;
thres_var := i-1;
end if;
end loop;
thres <= std_logic_vector(to_unsigned(thres_var, 32));
end if;
end process;
end Behavioral;
The declarations package is the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
package declarations is
--generic ( NHIST : integer := 6 );
type vector_array is array (23 downto 0) of std_logic_vector(7 downto 0);
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
end package declarations;
package body declarations is
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
end package body;
The testbench is the following:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench1 IS
END testbench1;
ARCHITECTURE behavior OF testbench1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT behavioral_code
port ( clk : in std_logic;
en : in std_logic;
hist : in vector_array;
--debug1 : out std_logic_vector ( 31 downto 0);
--debug10 : out std_logic_vector ( 31 downto 0);
--debug11 : out std_logic_vector ( 31 downto 0);
--debug2 : out std_logic_vector ( 31 downto 0);
--debug3 : out std_logic_vector ( 31 downto 0);
--debug4 : out std_logic_vector ( 31 downto 0);
--debug5 : out std_logic_vector ( 31 downto 0);
--debug6 : out std_logic_vector ( 31 downto 0);
--debug7 : out std_logic_vector ( 31 downto 0);
--debug8 : out std_logic_vector ( 31 downto 0);
--debug50 : out std_logic_vector ( 31 downto 0);
-- debug60 : out std_logic_vector ( 31 downto 0);
thres : out std_logic_vector ( 31 downto 0) );
end component;
--Inputs
signal en : std_logic := '0';
signal hist : vector_array := (others => '0');
signal clk: std_logic := '0';
--Outputs
signal thres : std_logic_vector(31 downto 0);
--signal debug1 : std_logic_vector(31 downto 0);
--signal debug10 : std_logic_vector(31 downto 0);
--signal debug11 : std_logic_vector(31 downto 0);
--signal debug2 : std_logic_vector ( 31 downto 0);
-- signal debug3 : std_logic_vector ( 31 downto 0);
--signal debug4 : std_logic_vector ( 31 downto 0);
--signal debug5 : std_logic_vector ( 31 downto 0);
--signal debug6 : std_logic_vector ( 31 downto 0);
-- signal debug7 : std_logic_vector ( 31 downto 0);
--signal debug8 : std_logic_vector ( 31 downto 0);
--signal debug50 : std_logic_vector ( 31 downto 0);
--signal debug60 : std_logic_vector ( 31 downto 0);
-- No clks detected in port list. Replace <clk> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: behavioral_code PORT MAP (
en => en,
clk => clk,
-- debug1 => debug1,
-- debug10 => debug10,
-- debug11 => debug11,
-- debug2 => debug2,
--debug3 => debug3,
--debug4 => debug4,
--debug5 => debug5,
--debug6 => debug6,
--debug7 => debug7,
--debug8 => debug8,
--debug50 => debug50,
--debug60 => debug60,
hist => hist,
thres => thres
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
en<='1';
--wait for <clk>_period*10;
-- insert stimulus here
wait;
end process;
END;
be aware that synthesis generates hardware out of your code. the code looks as if just "software programmed" and not intended for synthesis ;-)
e.g. a VHDL "for loop" generates the code within the block several times. therefore your code results in a veeeery large design. think of re-writing the code in a more sequential way. Use a
if rising_edge(clk) then
in your process to use FF-stages.
BTW: if you tested it with constants, your synthesizer tool most probably did the division for you and just implemented the result; that's why it worked with constants!
Following the suggestion in Baldy's answer to supply the missing clock edge statement, and supplying a guess at the contents of your missing package, I find that you omitted to supply the "divide" function.
So, restoring the intrinsic division, let's see what synthesis reports :
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multipliers : 2072
31x2-bit multiplier : 1
31x3-bit multiplier : 3
31x4-bit multiplier : 7
31x5-bit multiplier : 15
32x32-bit multiplier : 1986
33x32-bit multiplier : 60
# Adders/Subtractors : 4349
32-bit adder : 1373
32-bit adder carry in : 1984
32-bit subtractor : 992
# Adder Trees : 88
32-bit / 10-inputs adder tree : 1
...
32-bit / 7-inputs adder tree : 1
32-bit / 8-inputs adder tree : 1
32-bit / 9-inputs adder tree : 1
# Registers : 96
Flip-Flops : 96
# Comparators : 2077
32-bit comparator greater : 31
32-bit comparator lessequal : 62
...
64-bit comparator lessequal : 62
# Multiplexers : 61721
1-bit 2-to-1 multiplexer : 61536
32-bit 2-to-1 multiplexer : 185
=========================================================================
And then it goes on to take a considerable time attempting optimisations. But really synthesis has gone far enough to tell you what you need to know : This is indeed a very big design; far larger than the task justifies.
I can only concur with his suggestion that you have to reorganise the computation across multiple clock cycles until its size is acceptable. Then, synthesis time will also be reduced to acceptable limits.
Also ... All that logic with only 96 flipflops? This is a very unbalanced design and likely to be as slow as molasses. Pipeline registers - lots of them - will be required to achieve acceptable performance.