make -j behaves differently with and without sub makes - makefile

Question

Can someone explain why make with sub-makes has different parallelization behavior?
I have two examples below. In one, all targets are in one Makefile where as in the second example each target has its own folder/makefile and they call each other using $(MAKE).
Running them with -j produce outputs which are vastly different. In the first case, all access to the top-level dependency (a.out below) is synchronized. Make waits for the target to build before running any targets which depend on that.
In the second case, the top-level target (a.out below) is subjected to concurrent access. This causes serious problems for us unless we use our own synchronization techniques to overcome that.
Examples 1:
jesaremi#u16-3:~/maketest$ cat Makefile
.ONESHELL:
all: d.out b.out c.out a.out
a.out: CALLER ?= self
a.out:
#
echo entering $# "(called by $(CALLER))"
sleep 10
echo exiting $#
b.out: a.out
#
echo entering $#
sleep 1
echo exiting $#
c.out: a.out
#
echo entering $#
sleep 1
echo exiting $#
d.out: a.out
#
echo entering $#
sleep 1
echo exiting $#
jesaremi#u16-3:~/maketest$ make
entering a.out (called by self)
exiting a.out
entering d.out
exiting d.out
entering b.out
exiting b.out
entering c.out
exiting c.out
jesaremi#u16-3:~/maketest$ make -j
entering a.out (called by self)
exiting a.out
entering d.out
entering c.out
entering b.out
exiting c.out
exiting d.out
exiting b.out
Example 2 (using sub-make):
jesaremi#js-u16-1:~/maketest$ cat */Makefile
---------- a/Makefile -------------
.ONESHELL:
a.out: CALLER ?= self
a.out:
#
echo entering $# "(called by $(CALLER))"
sleep 10
echo exiting $#
---------- b/Makefile -------------
.ONESHELL:
export CALLER:=b
a.out:
$(MAKE) -C ../a
b.out: a.out
#
echo entering $#
sleep 1
echo exiting $#
---------- c/Makefile -------------
.ONESHELL:
export CALLER:=c
a.out:
$(MAKE) -C ../a
c.out: a.out
#
echo entering $#
sleep 1
echo exiting $#
---------- d/Makefile -------------
.ONESHELL:
export CALLER:=d
a.out:
$(MAKE) -C ../a
d.out: a.out
#
echo entering $#
sleep 1
echo exiting $#
jesaremi#js-u16-1:~/maketest$ cat Makefile
all: d.out c.out b.out a.out
%.out:
$(MAKE) -C $*
.PHONY:all
jesaremi#js-u16-1:~/maketest$ make
make -C d
make[1]: Entering directory '/home/jesaremi/maketest/d'
make -C ../a
make[2]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by d)
exiting a.out
make[2]: Leaving directory '/home/jesaremi/maketest/a'
make[1]: Leaving directory '/home/jesaremi/maketest/d'
make -C c
make[1]: Entering directory '/home/jesaremi/maketest/c'
make -C ../a
make[2]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by c)
exiting a.out
make[2]: Leaving directory '/home/jesaremi/maketest/a'
make[1]: Leaving directory '/home/jesaremi/maketest/c'
make -C b
make[1]: Entering directory '/home/jesaremi/maketest/b'
make -C ../a
make[2]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by b)
exiting a.out
make[2]: Leaving directory '/home/jesaremi/maketest/a'
make[1]: Leaving directory '/home/jesaremi/maketest/b'
make -C a
make[1]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by self)
exiting a.out
make[1]: Leaving directory '/home/jesaremi/maketest/a'
jesaremi#js-u16-1:~/maketest$ make -j
make -C d
make -C c
make -C b
make -C a
make[1]: Entering directory '/home/jesaremi/maketest/d'
make -C ../a
make[1]: Entering directory '/home/jesaremi/maketest/c'
make -C ../a
make[1]: Entering directory '/home/jesaremi/maketest/b'
make -C ../a
make[2]: Entering directory '/home/jesaremi/maketest/a'
make[1]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by self)
make[2]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by c)
make[2]: Entering directory '/home/jesaremi/maketest/a'
entering a.out (called by d)
entering a.out (called by b)
exiting a.out
make[1]: Leaving directory '/home/jesaremi/maketest/a'
exiting a.out
make[2]: Leaving directory '/home/jesaremi/maketest/a'
exiting a.out
make[1]: Leaving directory '/home/jesaremi/maketest/c'
make[2]: Leaving directory '/home/jesaremi/maketest/a'
make[1]: Leaving directory '/home/jesaremi/maketest/d'
exiting a.out
make[2]: Leaving directory '/home/jesaremi/maketest/a'
make[1]: Leaving directory '/home/jesaremi/maketest/b'

Answer 1

Perhaps you're thinking that recusive invocations of make communicate to each other which targets they are building and somehow interlock so that no two sub-makes are trying to build the same target at the same time.
That's nowhere close to something make can do. All make can do is notify other sub-makes how many targets they are building so that you are ensured that no more than N total targets (for -jN) are invoked.
If you want to ensure that two different makefiles don't try to build the same target, that's up to you to do by organizing your makefiles; make can't do it for you.
In the second example, you list all the prerequisites as a single target:
all: d.out c.out b.out a.out
This recipe says, "before all can be built the targets d.out, c.out, b.out, and a.out must be finished". This says nothing about the relative relationship between the prerequisites (d.out, c.out, b.out, or a.out) themselves so when you run with -j the sub-makes for all of them will be invoked at the same time. If each of those tries to build the same shared target, then they will interfere with each other.
If you want to ensure that doesn't happen you must declare the prerequisite relationship in your makefile so make knows about it. For example you could do this:
all: d.out c.out b.out a.out
d.out c.out b.out: a.out
%.out:
$(MAKE) -C $*
.PHONY:all
Now, the recipes to build d.out, c.out, and b.out won't be started until after the recipe to build a.out is complete.