I am getting vk: command not found when running vk, and getting bash: ./vk: No such file or directory when executing ./vk.
I did some research and the cause is usually that it isa 32bit exe on a 64bit machine
make builds the output to vk/_target. I cd to _target
When I run file vk I get this back.
vk: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), dynamically linked, interpreter /lib/ld6, not stripped
I have tried executing chmod +x vk and chmod u+x vk. I have tried every combination of typing ./vk and vk with chmod. I'm at a loss here. I have passed -m64 as an option to gcc, but that seems to be the default.
Here is my makefile
CFLAGS = -m64 -Wall -O3
CC = gcc
LINKER = ld -lc --entry main
DUMP = objdump
COPY = objcopy
TARGET_DIR = _target
SRCS := $(shell find ./ -name \*.c)
VPATH := $(sort $(dir $(SRCS)))
OBJS := $(patsubst %.c,$(TARGET_DIR)/%.o,$(notdir $(SRCS)))
$(TARGET_DIR)/vk : $(OBJS)
$(LINKER) $^ -o $#
$(DUMP) -D $# > $(#:=.list)
$(TARGET_DIR)/%.o : %.c folders
#echo "compiling $<"
$(CC) $(CFLAGS) -c $< -o $#
#echo "assembly dump $#"
$(DUMP) -D $# > $#.list
.PHONY: folders
folders:
mkdir -p $(TARGET_DIR)
.PHONY: clean
clean:
rm -rf $(TARGET_DIR)
Related
I am trying to write a Makefile since it's a good skill to have and all the times I've worked with them it all just seems like black magic to me.
The Makefile is shall mix C source and unit test in C++. I've looked at some examples and tried reading some guides but I am not getting it to work properly and most examples seems quite simple and doesn't really do what I would like to do.
This is the folder structure:
project
src
inc
unit_test
out
Here is my Makefile so far.
CXX = g++
CXXFLAGS = -g -c -I$(INC_DIR)
CC = gcc
CFLAGS = -g -c -Wall -Wextra -Wpedantic -I$(INC_DIR)
LIBS = -lcppunit
OUT_DIR = out
INC_DIR = inc
CPP_SRCS = $(wildcard unit_test/*.cpp)
CPP_OBJS = $(CPP_SRCS:unit_test/%.cpp=$(OUT_DIR)/%.o)
C_SRCS = $(wildcard src/*.c)
C_OBJS = $(C_SRCS:src/%.c=$(OUTDIR)/%.o)
BIN = $(OUT_DIR)/a.out
.PHONY: all run build clean
test:
#echo C_SRCS $(C_SRCS)
#echo C_OBJS $(C_OBJS)
#echo CPP_SRCS $(CPP_SRCS)
#echo CPP_OBJS $(CPP_OBJS)
all: run
run: build
./$(BIN)
build: $(BIN)
clean:
rm -f $(CPP_OBJS)
rm -f $(C_OBJS)
rm -f $(BIN)
$(BIN): $(C_OBJS) $(CPP_OBJS)
$(CXX) $(C_OBJS) $(CPP_OBJS) -o $# $(LIBS)
#echo "Build successful!"
$(CPP_OBJS): $(OUT_DIR)/%.o: unit_test/%.cpp
mkdir -p $(OUT_DIR)
#echo Compiling $<
$(CXX) $< $(CXXFLAGS) -o $#
$(C_OBJS): $(OUT_DIR)/%.o: src/%.c
#echo Compiling $<
$(CC) $< $(CFLAGS) -o $#
Here is the output of 'make test' which will describe my problem at this point in time.
C_SRCS src/add.c
C_OBJS /add.o
CPP_SRCS unit_test/Main.cpp unit_test/Tester.cpp
CPP_OBJS out/Main.o out/Tester.o
Why am I not getting the object file out/add.o when I am doing exactly the same for the the src folder as for the unit_test folder? What am I missing? It's not that obvious to me.
I was trying to compile some code written in c and c++ for an atmega32u4.
I wrote a makefile from information gathered from the internet, but it fails for some reason.
If I run the commands separately from the command line, they all work. However running the make command gives the following error:
main.cpp:3:10: fatal error: avr/io.h: No such file or directory
The contents of the main.cpp file are not really relevant, it's just a blink code.
The makefile looks like this:
all: init clean $(patsubst %.cpp, %.hex, $(wildcard *.cpp))
avr-size -A $(BUILDPATH)/*.elf
%.c.o: %.c
#mkdir -p $(BUILDPATH)
avr-gcc -c -g -Os -w -mmcu=$(CHIP) $^ -o $(BUILDPATH)/$#
%.cpp.o: %.cpp
#mkdir -p $(BUILDPATH)
avr-g++ -c -g -Os -w -mmcu=$(CHIP) $^ -o $(BUILDPATH)/$#
%.elf: %.o
avr-gcc -g -Os -w -mmcu=$(CHIP) $(BUILDPATH)/$^ -o $(BUILDPATH)/$#
%.hex: %.elf
avr-objcopy -R .eeprom --change-section-lma .eeprom=0 -O ihex $(BUILDPATH)/$^ $(BUILDPATH)/$#
So what am I doing wrong? Do I have to set up some environment variables or is the structure of the makefile incorrect?
I wrote a makefile which contains some wildcard target for building and running.
My makefile contents are the following.
ALL_EXES=$(shell ls *.exe 2>/dev/null)
.PHONY: all clean $(ALL_EXES) foo
CC=gcc
CFLAGS=-g -Wall
GTKFLAGS=$(shell pkg-config --cflags gtk+-3.0)
GTKLIBS=$(shell pkg-config --libs gtk+-3.0)
PWD=$(shell pwd)
clean:
#echo cleanning
$(shell sh -c "rm *.exe 2>/dev/null")
%: %.c
$(CC) $(GTKFLAGS) -o $# $< $(GTKLIBS) $(CFLAGS)
%.exe: %
#echo running $#
$(shell sh -c "$(PWD)/$#")
I can run make some-program successfully, but Nothing to be done for 'some-program.exe' is always occurs when I run make some-program.exe.
The line %: %.c should be %.exe: %.c , because that is the rule for creating a .exe file based on a .c source.
The line %.exe: % should be something else, e.g. run: foo.exe .
Finally, my workaround makefile is the followings.
ALL_EXES=$(shell ls *.exe 2>/dev/null)
.PHONY: all clean
CC=gcc
CFLAGS=-g -Wall
GTKFLAGS=$(shell pkg-config --cflags gtk+-3.0)
GTKLIBS=$(shell pkg-config --libs gtk+-3.0)
PWD=$(shell pwd)
clean:
#echo cleanning $(shell ls *.exe 2>/dev/null)
$(shell sh -c "rm *.exe 2>/dev/null")
%.exe: %.c
#echo building $<
$(CC) $(GTKFLAGS) -o $# $< $(GTKLIBS) $(CFLAGS)
run_%.exe: %.exe
#echo running $<
$(PWD)/$<
example-stack.exe: example-stack.c stack.c
$(CC) -I. -o $# $^ $(CFLAGS)
Running into trouble with libraries in makefiles again. Every time I try to get back into C make gives me a pain with libs.
make -pf /dev/null says the correct vars should be LDLIBS and LOADLIBES but the following doesn't alter the run command at all:
LOADLIBES=testing
LDFLAGS=testing
LDLIBS=testing
Needless to say this gives me errors because the -L flags don't end up in the command. Anyone know what's going on?
Full makefile below (Derivitave of Z Shaw's makefile)
OPTLIBS=$(xml2-config --libs)
OPTFLAGS=$(xml2-config --cflags)
STD=c99
CFLAGS=-std=$(STD) -g -O2 -Wall -Wextra -Isrc -rdynamic -DNDEBUG $(OPTFLAGS)
LDLIBS=-ldl $(OPTLIBS)
PREFIX?=/usr/local
SOURCES=$(wildcard src/**/*.c src/*.c)
OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
TEST_SRC=$(wildcard tests/*_tests.c)
TESTS=$(patsubst %.c,%,$(TEST_SRC))
TARGET=build/lib.a
SO_TARGET=$(patsubst %.a,%.so,$(TARGET))
# The Target Build
all: cls $(TARGET) $(SO_TARGET) tests
dev: CFLAGS=-std=$(STD) -g -Wall -Isrc -Wall -Wextra $(OPTFLAGS)
dev: all
$(TARGET): CFLAGS += -fPIC
$(TARGET): build $(OBJECTS)
ar rcs $# $(OBJECTS)
ranlib $#
$(SO_TARGET): $(TARGET) $(OBJECTS)
$(CC) -shared -o $# $(OBJECTS)
build:
#mkdir -p build
#mkdir -p bin
# The Unit Tests
$(TESTS): $(TARGET)
.PHONY: tests
tests: LDLIBS += $(TARGET)
tests: $(TESTS)
sh ./tests/runtests.sh
valgrind:
VALGRIND="valgrind --log-file=/tmp/valgrind-%p.log" $(MAKE)
# The Cleaner
clean: cls
rm -rf build $(OBJECTS) $(TESTS)
rm -f tests/tests.log
find . -name "*.gc*" -exec rm {} \;
rm -rf `find . -name "*.dSYM" -print`
# The Install
install: all
install -d $(DESTDIR)/$(PREFIX)/lib/
install $(TARGET) $(DESTDIR)/$(PREFIX)/lib/
# The Checker
BADFUNCS='[^_.>a-zA-Z0-9](str(n?cpy|n?cat|xfrm|n?dup|str|pbrk|tok|_)|stpn?cpy|a?sn?printf|byte_)'
check:
#echo Files with potentially dangerous functions.
#egrep $(BADFUNCS) $(SOURCES) || true
# Clear screen for unspammy terminals
cls:
ifdef TERM
clear
endif
You aren't using LDFLAGS, etc in your link command. Make that something along the lines of:
$(SO_TARGET): $(TARGET) $(OBJECTS)
$(CC) -shared $(LDFLAGS) -o $# $(OBJECTS) $(LDLIBS)
It tells the linker to link the dl library, which is located at /usr/lib/libdl.so. -l is the switch to add a library, dl is the name of it (without the lib prefix or .so extension).
This library includes functions for dynamically loading shared libraries.
I'm a little confused now. I'm trying to get the Makefile work but it breaks. I Hope someone can help me with this bad and frustrating time-killer.
I've written a small and lightweight part of a Compiler.
The project has the following structure:
/Compiler.cpp
/Makefile
/Buffer/
/Buffer/Makefile
/Scanner/
/Scanner/Makefile
/SymTable/
/SymTable/Makefile
When I'm compiling Buffer, Scanner and SymTable manual (changing the directory and typing 'make mode=release' it's no problem and each shared-library is compiled). But when I run the Makefile from within where the 'Master Makefile' /Makefile is, it fails and the terminal prints something like:
Buffer/libBuffer.so: file not recognized: File format not recognized
collect2: ld returned 1 exit status
make: \*** [Compiler] Error 1
Here is the listing of the Makefile of /Buffer/Makefile (the same for Scanner and SymTable):
CXX = g++
ifeq ($(mode),release)
CXXFLAGS = -g -fPIC -O3 -ffunction-sections -march=native
else
mode = debug
CXXFLAGS = -g3
endif
MODUL = Buffer
COMPONENTS = Buffer.h
MK_LIBRARY = lib$(MODUL).so
all: $(MK_LIBRARY)
$(MK_LIBRARY): $(COMPONENTS)
$(CXX) $(CXXFLAGS) -shared -o $# $^
clean:
rm -f $(MK_LIBRARY)
.PHONY: all
.PHONY: clean
The 'Master Makefile' looks like:
CXX = g++
ifeq ($(mode),release)
CXXFLAGS = -g -O3 -ffunction-sections -fwhole-program -march=native
else
mode = debug
CXXFLAGS = -g3
endif
TARGET = Compiler
COMPONENTS = $(TARGET)
DIRS = Buffer Scanner SymTable
MAKE = make
MFLAGS = mode=$(mode)
all: $(COMPONENTS)
$(TARGET): Compiler.cpp libBuffer.so libScanner.so libSymTable.so
$(CXX) $(CXXFLAGS) -IBuffer -IScanner -ISymTable \
-LBuffer -LScanner -LSymTable \
-lBuffer -lScanner -lSymTable -o $# Compiler.cpp
libBuffer.so: force_look
cd Buffer; $(MAKE) $(MFLAGS)
libScanner.so: force_look
cd Scanner; $(MAKE) $(MFLAGS)
libSymTable.so: force_look
cd SymTable; $(MAKE) $(MFLAGS)
clean:
rm -f $(COMPONENTS)
#for d in $(DIRS); do (cd $$d; $(MAKE) clean ); done
check:
#for d in $(DIRS); do (cd $$d; $(MAKE) check ); done
force_look:
true
.PHONY: all
.PHONY: clean
.PHONY: check
I hope some has an answer for me! Thanks!
There's something very weird about this part:
MODUL = Buffer
COMPONENTS = Buffer.h
MK_LIBRARY = lib$(MODUL).so
$(MK_LIBRARY): $(COMPONENTS)
$(CXX) $(CXXFLAGS) -shared -o $# $^
This rule tries to build libBuffer.so out of Buffer.h, the header file. How can this possibly work, without the definitions of the things in Buffer.cc? I would do it this way:
lib%.so: %.o
$(CXX) $(CXXFLAGS) -shared -o $# $^
EDIT:
You have the definitions of Buffer in Buffer.h? All right, you have more than one problem, and the only way to solve them is to do what almost always works: retreat to a simpler problem and solve that first. Can you make Buffer.o? And can you then link that into your executable (bypassing libBuffer.so)? And if not, can you write a "HelloWorld" in Buffer/, and link Buffer.o into that?