I have an old project with several C++ source and header files in a directory which are built in cygwin using GCC and a makefile. On editing the makefile to move all the temporary and output files into a sub-directory, the rules to build the object files didnt have any effect.
$(BIN): $(OBJ)
$(CXX) $(LDFLAGS) -o $(BIN) $^
%.o: %.c
$(CXX) $(INC) $(CXXFLAGS) $# -c -o $<
The following makefile still builds the output binary without having any rules to build the object files from source code.
INC=-I.
CXX=g++
CXXFLAGS=-std=c++11 -Wall -Wextra -Wconversion -pedantic -O2 -g
LDFLAGS=
CLEAN_FILES=*.o *.out *.stackdump *.exe *.gcno *.gcda
BIN=app
SRC=$(wildcard *.cpp)
OBJ=$(SRC:%.cpp=%.o)
all: $(BIN)
$(BIN): $(OBJ)
.PHONY: clean
clean:
rm -f $(CLEAN_FILES)
What is this automatic behavior called?
Two notes regarding built-in rules:
In large projects (which will have their owner rules for compiling, linking, ....), it might be easier to start with no built-in rules (make -r or make --no-builtin-rules).
Many built-in rules have hooks, via variables, that allow configuration changes. For example:
%.o: %.c:
$(COMPILE.c) $(OUTPUT_OPTION) $<
...
COMPILE.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
Where opssible to customize the command by modifying "CFLAGS", "CPPFLAGS", etc. Common examples will be make "CFLAGS=-O -g" to get optimized debug program, without having to redefine all the rules.
The set of rules that make knows about without you having to define them are called built-in rules. The manual lists most of them but not all of them. You can run make -p -f/dev/null to see a list of them all.
Related
I'm writing a small study project in C. I need to create a dynamic library and configure its use with macros. First, I create object files with the command:
$gcc -fPIC -c ../data_module/data_process.c
$gcc -fPIC -c ../data_libs/data_stat.c
Then I create a dynamic library like this:
$gcc -shared -o data_process.so data_process.o data_stat.o
And finally I build an executable file using this library:
$gcc main_executable_module.o ../data_libs/data_io.o ../yet_another_decision_module/decision.o -L. data_process.so -o test_main
It works and the executable works correctly. But there is a task to configure the library using macros:
Make the necessary changes to the code of the main_executable_module, configuring the use of the dynamic library using macros.
That is, if I understand correctly, you need to add macros to the main_executable_module.o so that you do not use the -L flags during assembly. But I can't find information anywhere on how to do it. Can you please tell me how to implement this or where can I read about it?
UPD: John Bollinger says
It is possible that the word "macros" is intended to be interpreted as makefile macros, which many people instead call (makefile) "variables". That would make this a question about make / makefiles, not about C.
My Makefile:
CC=gcc
LDFLAGS=
CFLAGS=-c -Wall -Wextra -Werror
SOURCES=main_executable_module.c ../data_libs/data_stat.c ../data_libs/data_io.c ../yet_another_decision_module/decision.c ../data_module/data_process.c
DYNLIB=../data_module/data_process.c
STAT=../data_libs/data_stat.c
BUILDDYN=main_executable_module.c ../data_libs/data_io.c ../yet_another_decision_module/decision.c
OBJECTS=$(SOURCES:.c=.o)
OBJBUILDDYN=$(BUILDDYN:.c=.o)
OBJDYNLIB=data_process.o
OBJDATASTAT=data_stat.o
EXECUTABLE=../../build/main
DEXECUTABLE=../../build/Quest_6
DLIBS=data_process.so
all: $(SOURCES) $(EXECUTABLE)
data_stat.a: $(OBJLIB) $(LIBS)
ar -rcs $(LIBS) $(OBJLIB)
data_process.so: $(OBJDYNLIB) $(OBJDATASTAT)
$(CC) -shared -o $(DLIBS) $(OBJDYNLIB) $(OBJDATASTAT)
$(OBJDYNLIB): $(DYNLIB)
$(CC) -fPIC -c $(DYNLIB)
$(OBJDATASTAT): $(STAT)
$(CC) -fPIC -c $(STAT)
build_with_dynamic:$(OBJECTS) $(EXECUTABLE)
$(CC) $(OBJBUILDDYN) -L. $(DLIBS) -o $(DEXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $#
.c.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm -rf $(EXECUTABLE) $(OBJECTS)
lclean:
rm -rf $(LEXECUTABLE) $(OBJECTS) $(LIBS) $(DEXECUTABLE)
rebuild: clean $(SOURCES) $(EXECUTABLE)
The results of the checks revealed nothing. There are two opinions about this task.
Leave everything as above. And in the file itself, add a header process.h. Then everything is assembled and working. And at the same time, if you change the code in the library, rebuild it, and do not rebuild the executable file, then the changes will be taken into account. That is, the idea of a dynamic library is respected.
Implement in such a way that there is no need to include headers in the main_executable_module.c. Then a special library is used for working with dynamic libraries, which allows you to write the path to the library and take individual functions from it. More about it here.
What was meant when it was said about macros, I still did not understand ...
I am brand new to make files in linux and trying to provide a make file for a simple heap management program.
When executing the make command, it works to originally build my program, however after making changes to the source file quickfit.c, make doesnt recognize the change and says "make: Nothing to be done for 'all'."
Why is it not recompiling my software after changes? I have all my source files in a source folder and all my header files in a include folder.
CC=gcc
CFLAGS= -Wall -w -g
INCLUDE:= -Iinclude/
SOURCE:= source/quickfit.c \
source/HeapTestEngine.o
EXE=QuickFit
all: $(EXE)
$(EXE):
$(CC) $(CFLAGS) $(INCLUDE) $(SOURCE) -o $(EXE)
$(EXE) doesn't depend on anything. make does not infer this dependency for you, you have to declare it.
$(EXE): $(SOURCE)
$(CC) $(CFLAGS) $(INCLUDE) $(SOURCE) -o $(EXE)
You'll probably also want to declare dependencies on your header files as well.
Note: it's a bit odd to consider an object file as "source". source/HeapTestEngine.o should probably have its own target.
Change:
$(EXE):
Into:
$(EXE): $(SOURCE)
I have a makefile with these rules.
all: $(TARGET)
OBJECTS = file.o
%.o: %.c
$(COMPILER) -c $(FLAGS) &< -o C_$(basename $#).o
%.o: %.s
$(COMPILER) -c $(FLAGS) &< -o S_$(basename $#).o
... The Linker is then called with *.o to link all the object files
I have the same filename file.c and file.s in a src directory. But make is only running the first rule for the object file. Why does it only compile once? And how can I get make to compile both file.c and file.s if they exist in my src folder?
I don't want to have to create a different object file name for a different extension. That would be silly.
Is there a way for me to compile the filename with the both .s and .c extension?
I feel like make can easily do this and I am missing something.
Thank you for the help. If I'm not clear please tell me and I will try to explain it more in depth.
You misunderstand how Make works.
There may be many ways to build a target; Make will use one of them, not all. Anyway, your makefile violates one of Mad Scientist's rules, in that your pattern rules do not build what they claim to build:
%.o: %.c
$(COMPILER) -c $(FLAGS) &< -o C_$(basename $#).o
%.o: %.s
$(COMPILER) -c $(FLAGS) &< -o S_$(basename $#).o
The first doesn't build foo.o, it builds C_foo.o; the second doesn't build foo.o, it builds S_foo.o. I don't know how your linking rule works, but if it depends on foo.o, you're in for trouble.
Try this:
C_%.o: %.c
$(COMPILER) -c $(FLAGS) &< -o $#
S_%.o: %.s
$(COMPILER) -c $(FLAGS) &< -o $#
Then give your linking rule whatever prerequisites you think it should have. If you want it to use both C_foo.o and S_foo.o (which doesn't sound like a good idea), then put both of them in the prerequisite list.
I am compiling some of my own FORTRAN code using a simple makefile but dislike having my code directory cluttered up with *.mod and *.o files.
Is there a simple way I can edit my makefile so that these compiled files are placed in a separate directory (something like ./obj/ )? I've searched through here and google to find a few examples but I can't get any of them working. Probably as I have very little experience of makefiles and fortran (have only coded C until now).
Below is my current makefile:
LIBBASE=/my/lib/dir/
HDF5LIB=$(LIBBASE)/hdf5/lib
HDF5INCLUDE=$(LIBBASE)/hdf5/include
MYLIB_LIB=$(LIBBASE)/mylib
MYLIB_INCLUDE=$(LIBBASE)/mylib
LIBS=-L$(HDF5LIB) -lhdf5 -lhdf5_fortran -lhdf5hl_fortran \
-L$(MYLIB_LIB) -lmylib
INC=-I./ -I$(HDF5INCLUDE) -I$(MYLIB_INCLUDE) -DINCLUDE_MYLIB
# Compiler
F90 = ifort
CC = ifort
FLAGS = -g -O2 -openmp
# ------ No machine-specific paths/variables after this -----
FSOURCE = my_structures my_constants my_utils my_prog MainMOD
OBJECTS = my_structures.o my_constants.o my_utils.o my_prog.o
all: $(FSOURCE)
MainMOD: MainMOD.F90
$(F90) $(FLAGS) -o $# $(INC) MainMOD.F90 $(LIBS) $(OBJECTS)
my_structures: my_structures.F90
$(F90) $(FLAGS) -c $(INC) imager_structures.F90 $(LIBS)
my_prog: my_prog.F90
$(F90) $(FLAGS) -c $(INC) my_prog.F90 $(LIBS)
my_constants: my_constants.F90
$(F90) $(FLAGS) -c $(INC) preproc_constants.F90 $(LIBS)
utils: my_utils.F90
$(F90) $(FLAGS) -c $(INC) my_utils.F90 $(LIBS)
clean:
rm -f $(FSOURCE) $(OBJECTS)
# Compilation rules
$(OBJ_DIR)\\%.o: %.F90
$(F90) $(FLAGS) -c $# $<
# Rule to prevent make from identifying Fortran .mod files as Modula2 source
# files
%.o : %.mod
First, the way Makefile works is based on that targets and sources are in the same directory. For sure, you can do the opposite, but Makefile wasn't designed with that option in mind so you'll have to make your recipes a bit ugly.
Now, if I really wanted to have object files in a separate directory and wasn't bounded by using make only, I'd use cmake which in contrast to make assumes that sources are separated from the build files.
If you still want to go with make, then I think you need to fix one thing.
From
$(OBJ_DIR)\\%.o: %.F90
to
$(OBJ_DIR)/%.o: %.F90
Also,
%.o : %.mod
is not required if you put
.SUFFIXES:
on the very first line of the file. This will turn off all implicit rules since you don't use them anyway.
I want to use the include directive only for a specific target. I do not want to run the other makefiles when the target is not needed because it means the makefiles are generated needlessly.
So is there a way to conditionally use the include directive, which is conditional on a target? Or somehow to make the include directive a prerequisite of a target.
Here's what I have so far:
# Flags
INCDIR = $(CURDIR)/include
CFLAGS = -Wall -Wno-overflow -Wno-uninitialized -pedantic -std=c99 -I$(INCDIR) -O3
LFLAGS = -flat_namespace -dynamiclib -undefined dynamic_lookup
# Directory names
# Set vpath search paths
vpath %.h include
vpath %.c src
vpath %.o build
vpath %.d build
# Get files for the core library
CORE_FILES = $(wildcard src/*.c)
CORE_OBJS = $(patsubst src/%.c, build/%.o, $(CORE_FILES))
CORE_DEPS = $(CORE_OBJS:.o=.d)
# Core library target linking
core : $(CORE_OBJS) | bin
$(CC) $(LFLAGS) -o bin/libcbitcoin.2.0.dylib $(CORE_OBJS)
# Include header prerequisites (How to do only for "core" target?)
include $(CORE_DEPS)
# Makefiles for header dependencies.
$(CORE_DEPS): build/%.d: src/%.c | build
rm -f $#; \
$(CC) -I$(INCDIR) -MM $< -MT '$(#:.d=.o) $#' > $#
# Objects depend on directory
$(CORE_OBS) : | build
# Create build directory
build:
mkdir build
# Create bin directory
bin:
mkdir bin
# Core Compilation
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
# Depencies require include/CBDependencies.h as a prerequisite
build/CBOpenSSLCrypto.o: include/CBDependencies.h
# Crypto library target linking
crypto : build/CBOpenSSLCrypto.o -lcrypto -lssl | bin
$(CC) $(LFLAGS) -o bin/libcbitcoin-crypto.2.0.dylib build/CBOpenSSLCrypto.o -lcrypto -lssl
# Crypto library compile
build/CBOpenSSLCrypto.o: dependencies/crypto/CBOpenSSLCrypto.c
$(CC) -c $(CFLAGS) $< -o $#
#Clean
clean:
rm -f $(CORE_OBJS) $(CORE_DEPS) build/CBOpenSSLCrypto.o
As you should be able to tell I do not need to include the ".d" files for "crypto" but I do for "core" (default goal).
Thank you for any help.
Make is not a procedural language, so treating it as one goes against the grain; your makefiles will be difficult to scale, and it can lead to subtle bugs.
There's a better way by Tom Tromey that's clean, efficient and scalable. The trick is to realize that you can build the dependency file in the same step as the object file. The dependencies simply tell Make when the object is due to be rebuilt; you don't need them when you first build the object, because Make knows that the object must be built. And if the dependencies change, that can only be because something in the source or the old dependencies has changed, so again Make knows that the object must be rebuilt. (This is not obvious, so it may take a little cogitation.)
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) -MM -MF build/$*.d $<
-include build/*.d
There's one more hitch: if you alter the code so as to remove a dependency -- and also remove that file -- you won't be able to rebuild, because the old dependency list will still demand a file which can no longer be found. The sophisticated solution is to process the dependency file so as to make each prerequisite (e.g. header) a target in its own right, with no commands, so that it can be assumed to be rebuilt when needed:
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) -MM -MF build/$*.d $<
#cp build/$*.d build/$*.P
#sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
-e '/^$$/ d' -e 's/$$/ :/' < build/$*.P >> build/$*.d;
#rm build/$*.P
A cruder method, but almost as foolproof, is to put in catch-all rules for headers and sources:
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) -MM -MF build/$*.d $<
%.cc %.h:
EDIT:
To break down the new commands:
The -MM option tells gcc to produce a make rule for the object file, instead of preprocessing or compiling. The default is to send the rule to wherever it would send preprocessed output, which will usually be stdout.
The -MF option, used with -MM, specifies the output file. So -MM -MF build/$*.d will put the rule where we want it.
So the following two commands are (almost always) equivalent:
$(CC) -MM -MF build/$*.d $<
$(CC) -MM $< > build/$*.d
(I've left out the -I$(...) and the possibility of using the -MMD option, because both get a little complicated and are not really the point of the question.)
You can use MAKECMDGOALS.
ifeq (core,$(MAKECMDGOALS))
include $(CORE_DEPS)
endif
You could of course, use ifneq (,$(findstring core,$(MAKECMDGOALS))) if there was a possibility of more than one target.
Note: this is a 'quick and dirty' solution -- I agree with Beta that you shouldn't make this a common practice (this could get messy if you did it in a lot of makefiles...).
John
I can't help breaking the guidelines for what is a good answer.
My answer to the original question is in my opinion, no you cannot include rules that are dependant on the target -all rules are processed before targets are considered. This is a limitation of make (I guess). Then again, good point, there is MAKECMDGOALS, but is this not just a hack in the make utility itself?
The answer from Beta is reasonable and orthodox enough, but you can't call it clean even if it is the best that can be done. It won't work if make has not processed the particular target before and the appropriate build/*.d dependency file is not sitting there.